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Thu, 05 Dec 2024 10:11:53 -0800 (PST) Received: from x1 ([192.210.17.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ef26ffb6f5sm3584572a91.6.2024.12.05.10.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 10:11:53 -0800 (PST) Date: Thu, 5 Dec 2024 10:11:50 -0800 From: Drew Fustini To: Emil Renner Berthing Cc: bigunclemax@gmail.com, Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] riscv: dts: thead: Fix TH1520 emmc and shdci clock rate Message-ID: References: <20241204111424.263055-1-bigunclemax@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241205_101155_451073_1C932B33 X-CRM114-Status: GOOD ( 23.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Dec 04, 2024 at 03:19:28PM +0000, Emil Renner Berthing wrote: > bigunclemax@ wrote: > > From: Maksim Kiselev > > > > In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci > > is 198Mhz. > > > > But changing from fixed-clock to CLK_EMMC_SDIO leads to increasing input > > clock from 198Mhz to 792Mhz. Because the CLK_EMMC_SDIO is actually 792Mhz. > > > > Therefore calculation of output SDCLK is incorrect now. > > The mmc driver sets the divisor to 4 times larger than it should be > > and emmc/sd works 4 times slower. > > > > This can be confirmed with fio test: > > Sequential read of emmc with fixed 198Mz clock: > > READ: bw=289MiB/s (303MB/s) > > > > Sequential read with CLK_EMMC_SDIO clock: > > READ: bw=82.6MiB/s (86.6MB/s) > > > > Let's fix this issue by providing fixed-factor-clock that divides > > CLK_EMMC_SDIO by 4 for emmc/sd nodes. > > Thanks for finding this bug! > > However, this feels like a work-around for a bug in the clock driver, and even > if there is a fixed factor divider somewhere this should probably be modelled > by the clock driver. Did you look into the documentation[1] and try to figure > out where eMMC clock comes from and where the /4 is missing? > > There is also a vendor tree somewhere with a much more complete clock driver. > Drew do you remember where it is? Maybe it's worth looking at how that driver > models the eMMC clocks. Sorry for the delay, I'm travelling until tomorrow. Maksim, thanks for finding this issue and sending a patch. That is a good point about checking the thead vendor kernel. I normally look at revy's thead-kernel repo [1] which is 5.10. revy also has a 6.6 lts branch in th1520-linux-kernel [2]. https://github.com/revyos/thead-kernel/tree/lpi4a/drivers/clk/thead Looking at line 454 in drivers/clk/thead/clk-light-fm.c [3]: clks[EMMC_SDIO_REF_CLK] = thead_light_clk_fixed_factor("emmc_sdio_ref_clk", "video_pll_foutpostdiv", 1, 4) /* Note: base clk is div 4 to 198M*/ Which derives from line 373: clks[VIDEO_PLL_FOUTPOSTDIV] = thead_clk_fixed("video_pll_foutpostdiv", 792000000); Thanks, Drew [1] https://github.com/revyos/thead-kernel [2] https://github.com/revyos/th1520-linux-kernel [3] https://github.com/revyos/thead-kernel/blob/lpi4a/drivers/clk/thead/clk-light-fm.c _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EF0F226EF2 for ; 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Thu, 05 Dec 2024 10:11:53 -0800 (PST) Received: from x1 ([192.210.17.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ef26ffb6f5sm3584572a91.6.2024.12.05.10.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 10:11:53 -0800 (PST) Date: Thu, 5 Dec 2024 10:11:50 -0800 From: Drew Fustini To: Emil Renner Berthing Cc: bigunclemax@gmail.com, Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] riscv: dts: thead: Fix TH1520 emmc and shdci clock rate Message-ID: References: <20241204111424.263055-1-bigunclemax@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Dec 04, 2024 at 03:19:28PM +0000, Emil Renner Berthing wrote: > bigunclemax@ wrote: > > From: Maksim Kiselev > > > > In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci > > is 198Mhz. > > > > But changing from fixed-clock to CLK_EMMC_SDIO leads to increasing input > > clock from 198Mhz to 792Mhz. Because the CLK_EMMC_SDIO is actually 792Mhz. > > > > Therefore calculation of output SDCLK is incorrect now. > > The mmc driver sets the divisor to 4 times larger than it should be > > and emmc/sd works 4 times slower. > > > > This can be confirmed with fio test: > > Sequential read of emmc with fixed 198Mz clock: > > READ: bw=289MiB/s (303MB/s) > > > > Sequential read with CLK_EMMC_SDIO clock: > > READ: bw=82.6MiB/s (86.6MB/s) > > > > Let's fix this issue by providing fixed-factor-clock that divides > > CLK_EMMC_SDIO by 4 for emmc/sd nodes. > > Thanks for finding this bug! > > However, this feels like a work-around for a bug in the clock driver, and even > if there is a fixed factor divider somewhere this should probably be modelled > by the clock driver. Did you look into the documentation[1] and try to figure > out where eMMC clock comes from and where the /4 is missing? > > There is also a vendor tree somewhere with a much more complete clock driver. > Drew do you remember where it is? Maybe it's worth looking at how that driver > models the eMMC clocks. Sorry for the delay, I'm travelling until tomorrow. Maksim, thanks for finding this issue and sending a patch. That is a good point about checking the thead vendor kernel. I normally look at revy's thead-kernel repo [1] which is 5.10. revy also has a 6.6 lts branch in th1520-linux-kernel [2]. https://github.com/revyos/thead-kernel/tree/lpi4a/drivers/clk/thead Looking at line 454 in drivers/clk/thead/clk-light-fm.c [3]: clks[EMMC_SDIO_REF_CLK] = thead_light_clk_fixed_factor("emmc_sdio_ref_clk", "video_pll_foutpostdiv", 1, 4) /* Note: base clk is div 4 to 198M*/ Which derives from line 373: clks[VIDEO_PLL_FOUTPOSTDIV] = thead_clk_fixed("video_pll_foutpostdiv", 792000000); Thanks, Drew [1] https://github.com/revyos/thead-kernel [2] https://github.com/revyos/th1520-linux-kernel [3] https://github.com/revyos/thead-kernel/blob/lpi4a/drivers/clk/thead/clk-light-fm.c