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[34.125.155.40]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f2ed644816sm16394234a91.25.2024.12.26.16.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Dec 2024 16:23:26 -0800 (PST) Date: Fri, 27 Dec 2024 00:23:22 +0000 From: Peilin Ye To: Xu Kuohai Cc: bpf@vger.kernel.org, Alexei Starovoitov , Eduard Zingerman , Song Liu , Yonghong Song , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , "Paul E. McKenney" , Puranjay Mohan , Catalin Marinas , Will Deacon , Quentin Monnet , Mykola Lysenko , Shuah Khan , Josh Don , Barret Rhoden , Neel Natu , Benjamin Segall , David Vernet , Dave Marchevsky , linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC bpf-next v1 2/4] bpf: Introduce load-acquire and store-release instructions Message-ID: References: <6ca65dc2916dba7490c4fd7a8b727b662138d606.1734742802.git.yepeilin@google.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Dec 26, 2024 at 11:07:10PM +0000, Peilin Ye wrote: > > > + if (BPF_ATOMIC_TYPE(insn->imm) == BPF_ATOMIC_LOAD) > > > + ptr = src; > > > + else > > > + ptr = dst; > > > + > > > + if (off) { > > > + emit_a64_mov_i(true, tmp, off, ctx); > > > + emit(A64_ADD(true, tmp, tmp, ptr), ctx); > > > > The mov and add instructions can be optimized to a single A64_ADD_I > > if is_addsub_imm(off) is true. > > Thanks! I'll try this. The following diff seems to work: --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -658,9 +658,15 @@ static int emit_atomic_load_store(const struct bpf_insn *insn, struct jit_ctx *c ptr = dst; if (off) { - emit_a64_mov_i(true, tmp, off, ctx); - emit(A64_ADD(true, tmp, tmp, ptr), ctx); - ptr = tmp; + if (is_addsub_imm(off)) { + emit(A64_ADD_I(true, ptr, ptr, off), ctx); + } else if (is_addsub_imm(-off)) { + emit(A64_SUB_I(true, ptr, ptr, -off), ctx); + } else { + emit_a64_mov_i(true, tmp, off, ctx); + emit(A64_ADD(true, tmp, tmp, ptr), ctx); + ptr = tmp; + } } if (arena) { emit(A64_ADD(true, tmp, ptr, arena_vm_base), ctx); I'll include it in the next version. I think the same thing can be done for emit_lse_atomic() and emit_ll_sc_atomic(); let me do that in a separate patch. Thanks, Peilin Ye