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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b417afsm62891955e9.36.2024.12.19.13.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 13:50:27 -0800 (PST) Date: Thu, 19 Dec 2024 21:50:26 +0000 From: Stafford Horne To: Joel Holdsworth Cc: Richard Henderson , "qemu-devel@nongnu.org" Subject: Re: [PATCH 2/2] hw/openrisc: Fixed undercounting of TTCR in continuous mode Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=shorne@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Dec 19, 2024 at 08:08:14PM +0000, Joel Holdsworth wrote: > > > > > + /* Zero the count by applying a negative offset to the counter */ > > > > > + or1k_timer->ttcr_offset += UINT32_MAX - (cpu->env.ttmr & TTMR_TP); > > > > > > > > Since UINT32_MAX is -1 in this context, this appears to be off-by-one. > > > > I think -(ttmr & mask) alone is correct. > > > > > > Thanks, I did send a mail to Joel asking about this bit. He didn't respond for 2 > > > weeks to I just sent the patch as is as it appears to work. As I understand, > > > yes UINT32_MAX is just -1. But why the -1? I guess it's because after > > > ttcr_offset is updated we call cpu_openrisc_timer_update() which calls > > > cpu_openrisc_count_update() to update ttcr. Since a few _ns would have passed > > > and we are rounding up it will update ttcr to 0. > > > > > > But maybe I am reading too much into it. > > > > I think you're reading too much into it -- I just think it's a bug which isn't particularly noticeable because the clock is only off by 1ns. > > Richard is correct. It should be: > > or1k_timer->ttcr_offset += -(cpu->env.ttmr & TTMR_TP); > > Stafford: sorry for not being responsive. I've been very busy lately, and it's been several months since I touched anything OpenRISC-related. Are you able to push this the rest of the way through the acceptance process? I had understood that you were looking for a more elaborate overhaul of the OpenRISC timer design which I haven't had time to work on. But if the patch can go forward in its current form, I think the improvement is worth having even it doesn't address other design issues. Hi Joel, Yes, I was able to sort out the issues and get everything tested and fixed up. The patch is now committed upstream in QEMU for the 9.2.0 release. I also thought its better to have this upstream in its current form rather than wait for further improvements. Thanks for your help. I look forward to you getting some free cycles and helping more with OpenRISC when you get any chance. I was also busy last year until November and didn't have much time to work on this. -Stafford