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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b9ac30e8a0sm1608974385a.63.2025.01.07.08.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 08:46:07 -0800 (PST) Date: Tue, 7 Jan 2025 11:46:04 -0500 From: Gregory Price To: Robert Richter Cc: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, "Fabio M. De Francesco" , Terry Bowman Subject: Re: [PATCH v1 03/29] cxl/pci: cxl_hdm_decode_init: Move comment Message-ID: References: <20250107141015.3367194-1-rrichter@amd.com> <20250107141015.3367194-4-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250107141015.3367194-4-rrichter@amd.com> On Tue, Jan 07, 2025 at 03:09:49PM +0100, Robert Richter wrote: > The comment applies to the check, move it there. > > Signed-off-by: Robert Richter > --- > drivers/cxl/core/pci.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index d206378c4cbc..c7050c13f71a 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -419,6 +419,15 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > if (!hdm) > return -ENODEV; > > + /* > + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base > + * [High,Low] when HDM operation is enabled the range register values > + * are ignored by the device, but the spec also recommends matching the > + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges > + * are expected even though Linux does not require or maintain that > + * match. If at least one DVSEC range is enabled and allowed, skip HDM > + * Decoder Capability Enable. > + */ I agree this comment applies to the earlier check, but wow this function is confusing when compared to what this comment says. For example this line /* * If the HDM Decoder Capability is already enabled then assume * that some other agent like platform firmware set it up. */ if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) return devm_cxl_enable_mem(&port->dev, cxlds); It seems like range register validation logic is unreachable if HDM decoders are enabled? It's unclear. > if (!info->mem_enabled) { > rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); > if (rc) > @@ -454,15 +463,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > return -ENXIO; > } > > - /* > - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base > - * [High,Low] when HDM operation is enabled the range register values > - * are ignored by the device, but the spec also recommends matching the > - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges > - * are expected even though Linux does not require or maintain that > - * match. If at least one DVSEC range is enabled and allowed, skip HDM > - * Decoder Capability Enable. > - */ > return 0; > } > EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL"); > -- > 2.39.5 >