Re: [PATCH net-next RFC 0/5] net: phy: Introduce a port representation

[Oleksij Rempel <o.rempel@pengutronix.de>]

On Tue, Jan 07, 2025 at 05:41:30PM +0100, Oleksij Rempel wrote:
> On Tue, Jan 07, 2025 at 05:22:51PM +0100, Andrew Lunn wrote:
> > >   I have however seen devices that have a 1G PHY connected to a RJ45
> > > port with 2 lanes only, thus limiting the max achievable speed to 100M.
> > > Here, we would explicietly describe the port has having 2 lanes. 
> 
> I can confirm existence of this kind of designs. One industrial real life
> example: a SoC connected to 3 port Gigabit KSZ switch. One port is
> typical RJ45 connector. Other port is RJ11 connector.
> 
> The speed can be reduced by using max-speed property. But i can't
> provide any user usable diagnostic information just by saying pair A or
> B is broken.
> 
> This is one of the reasons why i propose detailed description.

Here is one example:
https://www.balluff.com/de-de/products/BNI004F?gad_source=1&gclid=Cj0KCQiAvvO7BhC-ARIsAGFyToUmOy6VpSZUszHQ9X4tuUlyLdtAZqkk3tKxggF5z7D1pk3CgH5IOvwaAhhUEALw_wcB

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