From: Gregory Price <gourry@gourry.net>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Terry Bowman <terry.bowman@amd.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
Subject: Re: [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT
Date: Fri, 10 Jan 2025 17:48:35 -0500 [thread overview]
Message-ID: <Z4Gjw5LGTppFfuAC@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250107141015.3367194-26-rrichter@amd.com>
On Tue, Jan 07, 2025 at 03:10:11PM +0100, Robert Richter wrote:
> Add AMD platform specific Zen5 support for address translation.
>
> Zen5 systems may be configured to use 'Normalized addresses'. Then,
> CXL endpoints use their own physical address space and Host Physical
> Addresses (HPAs) need address translation from the endpoint to its CXL
> host bridge. The HPA of a CXL host bridge is equivalent to the System
> Physical Address (SPA).
>
Just adding the note that I've tested this patch set for HPA==SPA and
found it causes no regressions in my setup.
Still working on testing the normalized address mode due to a few BIOS
quirks I'm running up against.
~Gregory
next prev parent reply other threads:[~2025-01-10 22:48 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-07 14:09 [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Robert Richter
2025-01-07 14:09 ` [PATCH v1 01/29] cxl: Remove else after return Robert Richter
2025-01-07 16:10 ` Gregory Price
2025-01-07 16:37 ` Dave Jiang
2025-01-09 12:00 ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 02/29] cxl/pci: Moving code in cxl_hdm_decode_init() Robert Richter
2025-01-07 16:18 ` Gregory Price
2025-01-29 12:47 ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 03/29] cxl/pci: cxl_hdm_decode_init: Move comment Robert Richter
2025-01-07 16:46 ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 04/29] cxl/pci: Add comments to cxl_hdm_decode_init() Robert Richter
2025-01-07 16:51 ` Gregory Price
2025-01-13 16:47 ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 05/29] cxl/region: Move find_cxl_root() to cxl_add_to_region() Robert Richter
2025-01-07 16:49 ` Gregory Price
2025-01-13 16:52 ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 06/29] cxl/region: Factor out code to find the root decoder Robert Richter
2025-01-07 16:57 ` Gregory Price
2025-01-13 16:59 ` Jonathan Cameron
2025-01-29 13:13 ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 07/29] cxl/region: Factor out code to find a root decoder's region Robert Richter
2025-01-07 16:59 ` Gregory Price
2025-01-30 16:43 ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 08/29] cxl/region: Split region registration into an initialization and adding part Robert Richter
2025-01-07 18:29 ` Gregory Price
2025-01-30 16:53 ` Robert Richter
2025-01-09 1:08 ` Li Ming
2025-01-09 10:30 ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 09/29] cxl/region: Use iterator to find the root port in cxl_find_root_decoder() Robert Richter
2025-01-07 17:23 ` Gregory Price
2025-01-13 18:11 ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 10/29] cxl/region: Add function to find a port's switch decoder by range Robert Richter
2025-01-07 18:38 ` Gregory Price
2025-01-30 16:58 ` Robert Richter
2025-01-17 21:31 ` Ben Cheatham
2025-01-30 17:02 ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 11/29] cxl/region: Unfold cxl_find_root_decoder() into cxl_endpoint_initialize() Robert Richter
2025-01-07 18:41 ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 12/29] cxl: Modify address translation callback for generic use Robert Richter
2025-01-07 18:44 ` Gregory Price
2025-01-31 14:19 ` Robert Richter
2025-01-17 21:31 ` Ben Cheatham
2025-01-31 14:27 ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 13/29] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-01-07 18:47 ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 14/29] cxl: Introduce parent_port_of() helper Robert Richter
2025-01-07 18:50 ` Gregory Price
2025-01-13 18:20 ` Jonathan Cameron
2025-01-07 14:10 ` [PATCH v1 15/29] cxl/region: Use an endpoint's SPA range to find a region Robert Richter
2025-01-07 19:14 ` Gregory Price
2025-02-05 8:48 ` Robert Richter
2025-01-14 10:59 ` Jonathan Cameron
2025-01-31 15:46 ` Robert Richter
2025-01-17 21:31 ` Ben Cheatham
2025-02-05 9:00 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 16/29] cxl/region: Use translated HPA ranges to calculate the endpoint position Robert Richter
2025-01-07 22:01 ` Gregory Price
2025-02-05 10:38 ` Robert Richter
2025-01-17 21:31 ` Ben Cheatham
2025-02-05 10:43 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 17/29] cxl/region: Rename function to cxl_find_decoder_early() Robert Richter
2025-01-07 22:06 ` Gregory Price
2025-02-05 10:56 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 18/29] cxl/region: Avoid duplicate call of cxl_find_decoder_early() Robert Richter
2025-01-07 22:11 ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 19/29] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-01-07 22:18 ` Gregory Price
2025-02-06 10:50 ` Robert Richter
2025-01-17 21:31 ` Ben Cheatham
2025-02-06 11:03 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 20/29] cxl/region: Use translated HPA ranges " Robert Richter
2025-01-07 22:33 ` Gregory Price
2025-02-06 11:31 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 21/29] cxl/region: Lock decoders that need address translation Robert Richter
2025-01-07 22:35 ` Gregory Price
2025-02-06 13:23 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 22/29] cxl/region: Use translated HPA ranges to create a region Robert Richter
2025-01-07 23:08 ` Gregory Price
2025-02-06 13:25 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 23/29] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-01-13 17:48 ` Alison Schofield
2025-02-14 13:06 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 24/29] cxl/region: Use endpoint's SPA range to check " Robert Richter
2025-01-13 17:38 ` Alison Schofield
2025-02-14 13:09 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-01-07 16:32 ` Robert Richter
2025-01-07 23:28 ` Gregory Price
2025-01-08 14:52 ` Robert Richter
2025-01-08 15:49 ` Gregory Price
2025-01-08 15:48 ` Gregory Price
2025-01-09 10:14 ` Robert Richter
2025-01-14 11:13 ` Jonathan Cameron
2025-01-17 7:59 ` Robert Richter
2025-01-17 11:46 ` Jonathan Cameron
2025-01-17 14:10 ` Robert Richter
2025-01-09 22:25 ` Gregory Price
2025-01-15 15:05 ` Robert Richter
2025-01-15 17:05 ` Gregory Price
2025-01-15 22:24 ` Gregory Price
2025-01-17 14:06 ` Robert Richter
2025-01-10 22:48 ` Gregory Price [this message]
2025-01-17 8:41 ` Robert Richter
2025-01-17 21:32 ` Ben Cheatham
2025-01-28 9:29 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 26/29] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-01-07 14:10 ` [PATCH v1 27/29] cxl/region: Show message on registration failure Robert Richter
2025-01-07 23:11 ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 28/29] cxl/region: Show message on broken target list Robert Richter
2025-01-07 23:12 ` Gregory Price
2025-01-14 11:16 ` Jonathan Cameron
2025-02-06 21:23 ` Robert Richter
2025-02-07 17:51 ` Jonathan Cameron
2025-02-12 9:08 ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 29/29] cxl: Show message when a decoder was added to a port Robert Richter
2025-01-07 23:15 ` Gregory Price
2025-01-13 18:41 ` [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Alison Schofield
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