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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Jouni Högander" <jouni.hogander@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v3 06/10] drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB
Date: Fri, 17 Jan 2025 21:22:59 +0200	[thread overview]
Message-ID: <Z4quE2WnwYfiEIwT@intel.com> (raw)
In-Reply-To: <20250109073137.1977494-7-jouni.hogander@intel.com>

On Thu, Jan 09, 2025 at 09:31:33AM +0200, Jouni Högander wrote:
> Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do
> not check intel_dp->psr.lock being held when using DSB. This assertion
> doesn't make sense as in case of using DSB the actual write happens later
> and we are not taking intel_dp->psr.lock mutex over dsb commit.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c     | 16 ++++++++++------
>  drivers/gpu/drm/i915/display/intel_psr.h     |  4 +++-
>  3 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4271da219b41..5a5100f147a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7089,7 +7089,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
>  			intel_pipe_fastset(old_crtc_state, new_crtc_state);
>  	}
>  
> -	intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> +	intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state);
>  
>  	intel_atomic_update_watermarks(state, crtc);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 85ecedd3162d..1e99329b70a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2330,7 +2330,8 @@ static void intel_psr_force_update(struct intel_dp *intel_dp)
>  	intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);
>  }
>  
> -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
> +void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
> +					  const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -2344,20 +2345,23 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
>  					     crtc_state->uapi.encoder_mask) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
> -		lockdep_assert_held(&intel_dp->psr.lock);
> +		if (!dsb)
> +			lockdep_assert_held(&intel_dp->psr.lock);

The question now becomes what exactly that lock is protecting, why
is that important for the mmio path, and how is it not an issue
for the DSB path?

> +
>  		if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)
>  			return;
>  		break;
>  	}
>  
> -	intel_de_write(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder),
> -		       crtc_state->psr2_man_track_ctl);
> +	intel_de_write_dsb(display, dsb,
> +			   PSR2_MAN_TRK_CTL(display, cpu_transcoder),
> +			   crtc_state->psr2_man_track_ctl);
>  
>  	if (!crtc_state->enable_psr2_su_region_et)
>  		return;
>  
> -	intel_de_write(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
> -		       crtc_state->pipe_srcsz_early_tpt);
> +	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
> +			   crtc_state->pipe_srcsz_early_tpt);
>  }
>  
>  static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 956be263c09e..fc807817863e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -17,6 +17,7 @@ struct intel_crtc;
>  struct intel_crtc_state;
>  struct intel_display;
>  struct intel_dp;
> +struct intel_dsb;
>  struct intel_encoder;
>  struct intel_plane;
>  struct intel_plane_state;
> @@ -55,7 +56,8 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
>  bool intel_psr_enabled(struct intel_dp *intel_dp);
>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc);
> -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
> +void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
> +					  const struct intel_crtc_state *crtc_state);
>  void intel_psr_pause(struct intel_dp *intel_dp);
>  void intel_psr_resume(struct intel_dp *intel_dp);
>  bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state);
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

  parent reply	other threads:[~2025-01-17 19:23 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-09  7:31 [PATCH v3 00/10] PSR DSB support Jouni Högander
2025-01-09  7:31 ` [PATCH v3 01/10] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update Jouni Högander
2025-01-15  7:43   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 02/10] drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update Jouni Högander
2025-01-15  7:46   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 03/10] drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update Jouni Högander
2025-01-15  7:58   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 04/10] drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers Jouni Högander
2025-01-15  8:32   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 05/10] drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards Jouni Högander
2025-01-15  8:18   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 06/10] drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB Jouni Högander
2025-01-16  6:03   ` Manna, Animesh
2025-01-17 19:22   ` Ville Syrjälä [this message]
2025-01-20  6:47     ` Hogander, Jouni
2025-01-09  7:31 ` [PATCH v3 07/10] drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use Jouni Högander
2025-01-16  6:10   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 08/10] drm/i915/psr: Add intel_psr_is_psr_mode_changing Jouni Högander
2025-01-16  7:15   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 09/10] drm/i915/display: Don't use DSB if psr mode changing Jouni Högander
2025-01-16  7:19   ` Manna, Animesh
2025-01-09  7:31 ` [PATCH v3 10/10] drm/i915/psr: Allow DSB usage when PSR is enabled Jouni Högander
2025-01-16  7:27   ` Manna, Animesh
2025-01-17 20:20   ` Ville Syrjälä
2025-01-17 23:07     ` Ville Syrjälä
2025-01-20  7:28       ` Hogander, Jouni
2025-01-20 14:39         ` Ville Syrjälä
2025-01-20 15:27           ` Ville Syrjälä
2025-01-21 10:29           ` Hogander, Jouni
2025-01-21 13:57             ` Ville Syrjälä
2025-01-21 15:11             ` Ville Syrjälä
2025-01-22  5:53               ` Hogander, Jouni
2025-01-09  7:46 ` ✓ CI.Patch_applied: success for PSR DSB support (rev3) Patchwork
2025-01-09  7:46 ` ✓ CI.checkpatch: " Patchwork
2025-01-09  7:47 ` ✓ CI.KUnit: " Patchwork
2025-01-09  8:05 ` ✓ CI.Build: " Patchwork
2025-01-09  8:07 ` ✓ CI.Hooks: " Patchwork
2025-01-09  8:09 ` ✗ CI.checksparse: warning " Patchwork
2025-01-09  8:10 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-01-09  8:38 ` ✓ Xe.CI.BAT: success " Patchwork
2025-01-09  9:36 ` ✗ i915.CI.BAT: failure " Patchwork
2025-01-11 11:27 ` ✗ Xe.CI.Full: " Patchwork
2025-01-13 14:26 ` ✗ Fi.CI.SPARSE: warning for PSR DSB support (rev4) Patchwork
2025-01-13 15:02 ` ✓ i915.CI.BAT: success " Patchwork
2025-01-15  2:19 ` ✗ i915.CI.Full: failure " Patchwork

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