From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: linux-kernel@vger.kernel.org
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH v1 1/1] MAINTAINERS: Add pin control and GPIO to the Intel MID record
Date: Tue, 4 Feb 2025 19:37:17 +0200 [thread overview]
Message-ID: <Z6JQTdXEDWPaupZp@smile.fi.intel.com> (raw)
In-Reply-To: <20250204170100.48263-1-andriy.shevchenko@linux.intel.com>
On Tue, Feb 04, 2025 at 07:01:00PM +0200, Andy Shevchenko wrote:
> Intel MID record is not listed all related files. Add to there
> pin control and GPIO drivers along with HSU (High Speed UART)
> and HSU DMA.
Mika, JFYI, it's supposed to go via Intel pin control tree.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2025-02-04 17:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-04 17:01 [PATCH v1 1/1] MAINTAINERS: Add pin control and GPIO to the Intel MID record Andy Shevchenko
2025-02-04 17:37 ` Andy Shevchenko [this message]
2025-02-05 5:40 ` Mika Westerberg
2025-02-05 7:58 ` Andy Shevchenko
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