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d="scan'208";a="114382860" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 17 Feb 2025 10:12:55 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 20:12:54 +0200 Date: Mon, 17 Feb 2025 20:12:54 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ankit Nautiyal Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: Re: [PATCH 07/19] drm/i915/vrr: Prepare for fixed refresh rate timings Message-ID: References: <20250214121130.1808451-1-ankit.k.nautiyal@intel.com> <20250214121130.1808451-8-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250214121130.1808451-8-ankit.k.nautiyal@intel.com> X-Patchwork-Hint: comment X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Feb 14, 2025 at 05:41:17PM +0530, Ankit Nautiyal wrote: > Currently we always compute the timings as if vrr is enabled. > With this approach the state checker becomes complicated when we > introduce fixed refresh rate mode with vrr timing generator. > > To avoid the complications, instead of always computing vrr timings, we > compute vrr timings based on uapi.vrr_enable knob. > So when the knob is disabled we always compute vmin=flipline=vmax. > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 54 ++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 3bcf2a026ad3..a4ed102a2119 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -263,6 +263,35 @@ int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state) > intel_vrr_real_vblank_delay(crtc_state); > } > > +static > +int intel_vrr_fixed_rr_vmax(const struct intel_crtc_state *crtc_state) > +{ > + return intel_vrr_fixed_rr_vtotal(crtc_state); > +} > + > +static > +int intel_vrr_fixed_rr_vmin(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + > + return intel_vrr_fixed_rr_vtotal(crtc_state) - > + intel_vrr_flipline_offset(display); > +} > + > +static > +int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state) > +{ > + return intel_vrr_fixed_rr_vtotal(crtc_state); > +} > + > +static > +void intel_vrr_prepare_fixed_timings(struct intel_crtc_state *crtc_state) > +{ > + crtc_state->vrr.vmax = intel_vrr_fixed_rr_vmax(crtc_state); > + crtc_state->vrr.vmin = intel_vrr_fixed_rr_vmin(crtc_state); > + crtc_state->vrr.flipline = intel_vrr_fixed_rr_flipline(crtc_state); Same comment as to the previous patch: vblank delay is not a thing at this point, so this needs to just use the actual timings without any adjustments. The rest of the patch looks fine. > +} > + > static > int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) > { > @@ -343,6 +372,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > intel_vrr_compute_vrr_timings(crtc_state); > else if (is_cmrr_frac_required(crtc_state) && is_edp) > intel_vrr_compute_cmrr_timings(crtc_state); > + else > + intel_vrr_prepare_fixed_timings(crtc_state); > > if (HAS_AS_SDP(display)) { > crtc_state->vrr.vsync_start = > @@ -514,6 +545,13 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) > if (!crtc_state->vrr.enable) > return; > > + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), > + crtc_state->vrr.vmin - 1); > + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), > + crtc_state->vrr.vmax - 1); > + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), > + crtc_state->vrr.flipline - 1); > + > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), > TRANS_PUSH_EN); > > @@ -527,6 +565,20 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) > } > } > > +static > +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + > + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), > + intel_vrr_fixed_rr_vmin(crtc_state) - 1); > + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), > + intel_vrr_fixed_rr_vmax(crtc_state) - 1); > + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), > + intel_vrr_fixed_rr_flipline(crtc_state) - 1); > +} > + > void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > { > struct intel_display *display = to_intel_display(old_crtc_state); > @@ -541,6 +593,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > TRANS_VRR_STATUS(display, cpu_transcoder), > VRR_STATUS_VRR_EN_LIVE, 1000); > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); > + > + intel_vrr_set_fixed_rr_timings(old_crtc_state); > } > > static > -- > 2.45.2 -- Ville Syrjälä Intel