From: Zhao Liu <zhao1.liu@intel.com>
To: Babu Moger <babu.moger@amd.com>
Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org,
davydov-max@yandex-team.ru
Subject: Re: [PATCH v5 6/6] target/i386: Add support for EPYC-Turin model
Date: Thu, 20 Feb 2025 20:11:54 +0800 [thread overview]
Message-ID: <Z7ccCtbPPuRRdGUN@intel.com> (raw)
In-Reply-To: <3d918a6327885d867f89aa2ae4b4a19f0d5fb074.1738869208.git.babu.moger@amd.com>
> +static const CPUCaches epyc_turin_cache_info = {
> + .l1d_cache = &(CPUCacheInfo) {
> + .type = DATA_CACHE,
> + .level = 1,
> + .size = 48 * KiB,
> + .line_size = 64,
> + .associativity = 12,
> + .partitions = 1,
> + .sets = 64,
> + .lines_per_tag = 1,
> + .self_init = 1,
true.
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l1i_cache = &(CPUCacheInfo) {
> + .type = INSTRUCTION_CACHE,
> + .level = 1,
> + .size = 32 * KiB,
> + .line_size = 64,
> + .associativity = 8,
> + .partitions = 1,
> + .sets = 64,
> + .lines_per_tag = 1,
> + .self_init = 1,
true.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
(And it would be better to add a Turin entry in docs/system/cpu-models-x86.rst.inc
later :-).)
Thanks,
Zhao
next prev parent reply other threads:[~2025-02-20 11:52 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 19:28 [PATCH v5 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model Babu Moger
2025-02-06 19:28 ` [PATCH v5 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits Babu Moger
2025-02-20 10:59 ` Zhao Liu
2025-02-25 17:01 ` John Allen
2025-02-26 20:28 ` Moger, Babu
2025-02-27 6:42 ` Zhao Liu
2025-02-06 19:28 ` [PATCH v5 2/6] target/i386: Update EPYC-Rome " Babu Moger
2025-02-20 11:18 ` Zhao Liu
2025-02-21 0:41 ` Moger, Babu
2025-02-06 19:28 ` [PATCH v5 3/6] target/i386: Update EPYC-Milan " Babu Moger
2025-02-20 11:26 ` Zhao Liu
2025-02-21 0:43 ` Moger, Babu
2025-02-06 19:28 ` [PATCH v5 4/6] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing Babu Moger
2025-02-20 12:00 ` Zhao Liu
2025-02-21 0:45 ` Moger, Babu
2025-02-06 19:28 ` [PATCH v5 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits Babu Moger
2025-02-20 12:05 ` Zhao Liu
2025-02-21 0:46 ` Moger, Babu
2025-02-21 0:46 ` Moger, Babu
2025-02-06 19:28 ` [PATCH v5 6/6] target/i386: Add support for EPYC-Turin model Babu Moger
2025-02-20 12:11 ` Zhao Liu [this message]
2025-02-21 0:48 ` Moger, Babu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z7ccCtbPPuRRdGUN@intel.com \
--to=zhao1.liu@intel.com \
--cc=babu.moger@amd.com \
--cc=davydov-max@yandex-team.ru \
--cc=kvm@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.