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Thu, 20 Feb 2025 10:23:02 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7328acf354esm6281724b3a.3.2025.02.20.10.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 10:23:02 -0800 (PST) Date: Thu, 20 Feb 2025 10:23:00 -0800 From: Deepak Gupta To: Chunyan Zhang Cc: =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Chunyan Zhang , Palmer Dabbelt , Albert Ou , Paul Walmsley , Alexandre Ghiti , Andrew Morton , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Alistair Popple , linux-mm@kvack.org Subject: Re: [PATCH V5 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Message-ID: References: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> <20241113095833.1805746-2-zhangchunyan@iscas.ac.cn> <87frl0snf6.fsf@all.your.base.are.belong.to.us> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_102304_447567_CB7DB23D X-CRM114-Status: GOOD ( 19.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sorry for the late response. On Tue, Feb 11, 2025 at 04:05:02PM +0800, Chunyan Zhang wrote: >On Tue, 11 Feb 2025 at 12:01, Deepak Gupta wrote: >> >> On Tue, Feb 11, 2025 at 09:20:22AM +0800, Chunyan Zhang wrote: >> >On Thu, 30 Jan 2025 at 16:42, Bj=F6rn T=F6pel wrote: >> >> >> >> Chunyan Zhang writes: >> >> >> >> > The PTE bit(9) on RISC-V is reserved for software, it is used by de= vmap >> >> > now which has to be disabled if we want to use bit(9) for other fea= tures, >> >> > since there's no more free PTE bit on RISC-V now. >> >> > >> >> > So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as >> >> > the build condition of devmap definitions. >> >> >> >> Heads-up: It seems like Alistair's series [1] that removes the devmap >> >> PTE bit will most likely land in 6.15. >> > >> >Yes, I've been keeping an eye on Alistair's series, intended to update >> >this patchset after Alistair's patch that removes the devmap PTE bit >> >got merged. >> >> Please keep in mind that even after claiming back devmap PTE SW bit, a c= ompile >> time decision to select between uffd-wp and soft-dirty is not desirable. > >Yes, I agree. I've read your aother email. I also hope we can have >more RSW bits to use. So should we add uffd-wp and soft-dirty support >on RISC-V until we have two RSW bits for these two functions? Is an >undesirable solution better than no solution for now? Problem is that this undesirable solution doesn't solve anything for *most*= users. Kernel can't deviate from providing functionality (which is actually arch-a= gnostic) to user mode depending on the architecture. >I can optimize the code when we have more free RSW bits, that's not hard. We got 3 use cases, - pfnmap/pte_special - uffd-wp - softdirty 4th one for devmap, I hope we don't need to do it. Should get it back. https://lore.kernel.org/lkml/cover.95ff0627bc727f2bae44bea4c00ad7a83fbbcfac= .1739941374.git-series.apopple@nvidia.com/#r It looks like any work there would be wasted time. There is a (fast track) proposal out there to get 2 more RSW bits. https://lists.riscv.org/g/tech-privileged/message/2268 I hope it gets ratified soon. We will have proper solution to this problem = then. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F0EEC021B2 for ; Thu, 20 Feb 2025 18:23:08 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 0AA30280305; Thu, 20 Feb 2025 13:23:08 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 032C3280304; Thu, 20 Feb 2025 13:23:07 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id E15C5280305; Thu, 20 Feb 2025 13:23:07 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id C05DB280304 for ; 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Thu, 20 Feb 2025 10:23:02 -0800 (PST) Date: Thu, 20 Feb 2025 10:23:00 -0800 From: Deepak Gupta To: Chunyan Zhang Cc: =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Chunyan Zhang , Palmer Dabbelt , Albert Ou , Paul Walmsley , Alexandre Ghiti , Andrew Morton , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Alistair Popple , linux-mm@kvack.org Subject: Re: [PATCH V5 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Message-ID: References: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> <20241113095833.1805746-2-zhangchunyan@iscas.ac.cn> <87frl0snf6.fsf@all.your.base.are.belong.to.us> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 3D5D4140011 X-Stat-Signature: h1q9578o8aqshw859csedkoswkpzcb9f X-Rspam-User: X-HE-Tag: 1740075784-106165 X-HE-Meta: U2FsdGVkX187qxc5V23QECn9Da6VnbrhESn9Q54VScZzciY61nOC+cjRW46dAoDY/bTSVg+inhQ97FCF4B0gcl3oHkVURxImG818JtbSZRQIOaVH65vVoF6O9xYn9Ea7m8dO+aidsZkhYoPuynfoP69VFOO4HLtcOgXT1aoElAY/tyzb9eTM+AkqYiygkcrGJZn+WX7DUe0QJCiYNzm6tbBzPrzedLw2zp1keWejT48y+D663ZNCaEA4l+k73Fxc/c0WzSvXJwJi03O6MbIFgO6pOHfkR59xnMeT9co1KwVlahosqzbJq8FT4K8cf6HzVq6GmlZTmV9AD2rzVF3xaHX0TJtTrC6/+B8rz4usp/gFCO0RXJIiPJkGU6kJhhcPTwgQe3dgi6M8P7FQ6HhLP7ngd1TzQg2eKUxVQu0AHcuZpM0DUOxxVName2qF4pjAz/G9bbLYtbRp2rgd5YuTAiqwm4dBPFK5qD2sP2BFW5XFE4vYgw32V0xWf+hiyL6Ea9GoMA1UQ30NlBsR7BqURn5lZYfdwqG7BZIAUdJw6V7Bqo6Xeion1gHUAf871eMvA8BiYRn8aeAjY5lQ3zrPnwJO2ny91YMP97sBqsWtLNoe7YQcY+jhW99twShJGKQJBqrL5BoMyHnN1pkhhvL32a+F1VpxsaOpl9kdigxhS5UFAo09Vf3LeBtyOg/Ij0L38g6e2jEiEwqPLsRuSdqFTJa3TgeE5Pd5qAlnP5WSOUT0t/QKdykzQ6ChvR3yoO42s83lQoni7S9D8bopexw0blQRNccJKazRtsyQ36EuCb/4f2GJmjenyU785EWeYGdodwdV4boG/+njgAH+q8TuFC/TzcRZ+8M2HE3Qm98mj0aMojP7mY1N8iHAUYuooij3eRHQpoh6tr+noxFSpTH3XeN+0f9v1/4HOCnpyNYM7oVF1qSbWLiOvj5cxHGRBVzp7Mw3MsYOlapdGZhV/h/ N8GKjHmc SkBJyD/OVjJlYBxjzW6jrUm9MVFvP6xI+3rb6UkO/Mq8jXtEM1DEOUYPBUciD2C5uXOrL6MUjdqksS/RRdr/aRJ11kmGrVa1zDNBG4sxoD8xre8vp9HXdT/hYBjc9ZVkMxRzSzIc9ixpluCBw0AMsP0MngMg1WhPTvOkF65MwaEMHJBlWOB2OhMSzi/sLMGuMWAQyLJKh4aOINrGvRu+UM2GibIlQiC3pWkWJXiajDChozaTTVRWog0jynQj9OnVODxdVPbYw0AXntnFGwEtTRaYm1I4/BzNfvXZBW5nw93p6v7ngIeLFnm64694tVH8/2q8ZdOPE37l/g1lx4EORwJy6EUnYApYcxBSyEHzxapXbjxUX3ejWX4J3nD4VF5wRlONuqMqtbnIzXNhgalNnaS6DS/zNo9ETvD5eutS4Rm8gd5Y1zCDsUPOQXN62rSG4OpR9Q1LXQjtZPT2A/pC5hwKzylNmOGIAH314vY98M5HrxhXOKwZRZ83EwT8RlzHzZ51XXFye60h2qgezBj21sZ0/6WGqNEqDUTKR9MpjL5rSutweUTzaLVz7PnLBGwi8i72XBTRWdRopyinONvCXXOmdv2yQfWcEFpdjv0FVhikBmvhLRcYW1YI8Og== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000001, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Sorry for the late response. On Tue, Feb 11, 2025 at 04:05:02PM +0800, Chunyan Zhang wrote: >On Tue, 11 Feb 2025 at 12:01, Deepak Gupta wrote: >> >> On Tue, Feb 11, 2025 at 09:20:22AM +0800, Chunyan Zhang wrote: >> >On Thu, 30 Jan 2025 at 16:42, Björn Töpel wrote: >> >> >> >> Chunyan Zhang writes: >> >> >> >> > The PTE bit(9) on RISC-V is reserved for software, it is used by devmap >> >> > now which has to be disabled if we want to use bit(9) for other features, >> >> > since there's no more free PTE bit on RISC-V now. >> >> > >> >> > So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as >> >> > the build condition of devmap definitions. >> >> >> >> Heads-up: It seems like Alistair's series [1] that removes the devmap >> >> PTE bit will most likely land in 6.15. >> > >> >Yes, I've been keeping an eye on Alistair's series, intended to update >> >this patchset after Alistair's patch that removes the devmap PTE bit >> >got merged. >> >> Please keep in mind that even after claiming back devmap PTE SW bit, a compile >> time decision to select between uffd-wp and soft-dirty is not desirable. > >Yes, I agree. I've read your aother email. I also hope we can have >more RSW bits to use. So should we add uffd-wp and soft-dirty support >on RISC-V until we have two RSW bits for these two functions? Is an >undesirable solution better than no solution for now? Problem is that this undesirable solution doesn't solve anything for *most* users. Kernel can't deviate from providing functionality (which is actually arch-agnostic) to user mode depending on the architecture. >I can optimize the code when we have more free RSW bits, that's not hard. We got 3 use cases, - pfnmap/pte_special - uffd-wp - softdirty 4th one for devmap, I hope we don't need to do it. Should get it back. https://lore.kernel.org/lkml/cover.95ff0627bc727f2bae44bea4c00ad7a83fbbcfac.1739941374.git-series.apopple@nvidia.com/#r It looks like any work there would be wasted time. There is a (fast track) proposal out there to get 2 more RSW bits. https://lists.riscv.org/g/tech-privileged/message/2268 I hope it gets ratified soon. We will have proper solution to this problem then.