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Mon, 03 Mar 2025 06:10:02 -0800 (PST) Date: Mon, 3 Mar 2025 15:09:56 +0100 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Jiqian Chen Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini , Oleksii Kurochko , Anthony PERARD , Michal Orzel , Huang Rui Subject: Re: [PATCH v9] vpci: Add resizable bar support Message-ID: References: <20250224032433.1879630-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250224032433.1879630-1-Jiqian.Chen@amd.com> On Mon, Feb 24, 2025 at 11:24:33AM +0800, Jiqian Chen wrote: > Some devices, like AMDGPU, support resizable bar capability, > but vpci of Xen doesn't support this feature, so they fail > to resize bars and then cause probing failure. > > According to PCIe spec, each bar that supports resizing has > two registers, PCI_REBAR_CAP and PCI_REBAR_CTRL. So, add > handlers to support resizing the size of BARs. > > Note that Xen will only trap PCI_REBAR_CTRL, as PCI_REBAR_CAP > is read-only register and the hardware domain already gets > access to it without needing any setup. > > Signed-off-by: Jiqian Chen Reviewed-by: Roger Pau Monné Just one question below about a cosmetic adjustment. > diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h > index 250ba106dbd3..2f1d0d63e962 100644 > --- a/xen/include/xen/pci_regs.h > +++ b/xen/include/xen/pci_regs.h > @@ -459,6 +459,7 @@ > #define PCI_EXT_CAP_ID_ARI 14 > #define PCI_EXT_CAP_ID_ATS 15 > #define PCI_EXT_CAP_ID_SRIOV 16 > +#define PCI_EXT_CAP_ID_REBAR 21 /* Resizable BAR */ > > /* Advanced Error Reporting */ > #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ > @@ -541,6 +542,20 @@ > #define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) > #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) > > +/* Resizable BARs */ > +#define PCI_REBAR_CAP(n) (4 + 8 * (n)) /* capability register */ > +#define PCI_REBAR_CAP_SIZES_MASK 0xFFFFFFF0U /* supported BAR sizes in CAP */ > +#define PCI_REBAR_CTRL(n) (8 + 8 * (n)) /* control register */ > +#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ > +#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ > +#define PCI_REBAR_CTRL_BAR_SIZE 0x00003F00 /* BAR size */ > +#define PCI_REBAR_CTRL_SIZES_MASK 0xFFFF0000U /* supported BAR sizes in CTRL */ > + > +#define PCI_REBAR_CTRL_SIZE_BIAS 20 > +#define PCI_REBAR_CTRL_SIZE(v) \ > + (1ULL << (MASK_EXTR(v, PCI_REBAR_CTRL_BAR_SIZE) \ > + + PCI_REBAR_CTRL_SIZE_BIAS)) I think this could fit on a single line if the indent was just 4 spaces. Would you mind me adjusting it at commit if it fits? Thanks, Roger.