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Wed, 05 Mar 2025 22:12:32 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a7f75dsm4221555ad.122.2025.03.05.22.12.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 22:12:32 -0800 (PST) Date: Wed, 5 Mar 2025 22:12:30 -0800 From: Deepak Gupta To: Alistair Francis Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Adam Zabrocki Subject: Re: [PATCH 1/2] target/riscv: fix access permission checks for CSR_SSP Message-ID: References: <20250218025446.2452254-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=debug@rivosinc.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Thu, Mar 06, 2025 at 03:20:55PM +1000, Alistair Francis wrote: >On Tue, Feb 18, 2025 at 12:56 PM Deepak Gupta wrote: >> >> Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for >> zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access >> to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But >> rather rules clearly specified in section "2.2.4. Shadow Stack Pointer" > >Do you mean "22.2.1. Shadow Stack Pointer (ssp) CSR access contr" in >the priv spec? No I meant 2.2.4 of zicfiss specification. Section 22.2.1 of priv spec says same. > >> of `zicfiss` specification. Thanks to Adam Zabrocki for bringing this >> to attention. > >The thanks should probably be below the line Sure > >> >> Fixes: 8205bc127a83 ("target/riscv: introduce ssp and enabling controls >> for zicfiss" >> >> Reported-by: Adam Zabrocki >> Signed-off-by: Deepak Gupta > >The actual change looks good: > >Reviewed-by: Alistair Francis > >Alistair > >> --- >> target/riscv/csr.c | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index afb7544f07..75c661d2a1 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -191,6 +191,11 @@ static RISCVException cfi_ss(CPURISCVState *env, int csrno) >> return RISCV_EXCP_ILLEGAL_INST; >> } >> >> + /* If ext implemented, M-mode always have access to SSP CSR */ >> + if (env->priv == PRV_M) { >> + return RISCV_EXCP_NONE; >> + } >> + >> /* if bcfi not active for current env, access to csr is illegal */ >> if (!cpu_get_bcfien(env)) { >> #if !defined(CONFIG_USER_ONLY) >> -- >> 2.34.1 >> >>