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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 19:45:35.1144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a707e251-0063-4339-880a-08dd5ce77690 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5781 Received-SPF: softfail client-ip=40.107.102.83; envelope-from=nicolinc@nvidia.com; helo=NAM04-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Mar 06, 2025 at 04:59:39PM +0100, Eric Auger wrote: > >>> +++ b/include/system/host_iommu_device.h > >>> @@ -22,10 +22,16 @@ > >>> * > >>> * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this > >> represents > >>> * the @out_capabilities value returned from IOMMU_GET_HW_INFO > >> ioctl) > >>> + * > >>> + * @nesting: nesting page table support. > >>> + * > >>> + * @fs1gp: first stage(a.k.a, Stage-1) 1GB huge page support. > >>> */ > >>> typedef struct HostIOMMUDeviceCaps { > >>> uint32_t type; > >>> uint64_t hw_caps; > >>> + bool nesting; > >>> + bool fs1gp; > >> this looks quite vtd specific, isn't it? Shouldn't we hide this is a > >> vendor specific cap struct? > > Yes? I guess ARM hw could also provide nesting support at least > > There are some reasons I perfer a flatten struct even if some > > Elements may be vendor specific. > > 1. If a vendor doesn't support an capability for other vendor, > > corresponding element should be zero by default. > > 2. An element vendor specific may become generic in future > > and we don't need to update the structure when that happens. > > 3. vIOMMU calls get_cap() to query if a capability is supported, > > so a vIOMMU never query a vendor specific capability it doesn't > > recognize. Even if that happens, zero is returned hinting no support. > I will let others comment but in general this is frown upon and unions > are prefered at least. Yea, it feels odd to me that we stuff vendor specific thing in the public structure. It's okay if we want to store in HostIOMMUDeviceCaps the vendor specific data pointer (opaque), just for convenience. I think we can have another PCIIOMMUOps op for vendor code to run iommufd_backend_get_device_info() that returns the hw_caps for the core code to read. Or perhaps the vendor code can just return a HWPT directly? If IOMMU_HW_CAP_DIRTY_TRACKING is set in the hw_caps, the vendor code can allocate a HWPT for that. And if vendor code detects the "nesting" cap in vendor struct, then return a nest_parent HWPT. And returning NULL can let core code allocate a default HWPT (or just attach the device to IOAS for auto domain/hwpt). I am also hoping that this can handle a shared S2 nest_parent HWPT case. Could the core container structure or so store the HWPT? Thanks Nicolin