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Tue, 11 Mar 2025 11:11:14 -0700 (PDT) Received: from andrea ([31.189.82.201]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac2929390b4sm453700066b.75.2025.03.11.11.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 11:11:14 -0700 (PDT) Date: Tue, 11 Mar 2025 19:11:10 +0100 From: Andrea Parri To: =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Cc: Andy Chiu , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, bjorn@rivosinc.com, puranjay12@gmail.com, alexghiti@rivosinc.com, yongxuan.wang@sifive.com, greentime.hu@sifive.com, nick.hu@sifive.com, nylon.chen@sifive.com, tommy.wu@sifive.com, eric.lin@sifive.com, viccent.chen@sifive.com, zong.li@sifive.com, samuel.holland@sifive.com Subject: Re: [PATCH v3 6/7] riscv: add a data fence for CMODX in the kernel mode Message-ID: References: <20241127172908.17149-1-andybnac@gmail.com> <20241127172908.17149-7-andybnac@gmail.com> <87ldtck8k0.fsf@all.your.base.are.belong.to.us> <87ldtbwrdb.fsf@all.your.base.are.belong.to.us> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87ldtbwrdb.fsf@all.your.base.are.belong.to.us> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250311_111116_994675_2B56F3F0 X-CRM114-Status: GOOD ( 14.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Mar 11, 2025 at 03:53:36PM +0100, Bj=F6rn T=F6pel wrote: > Andrea Parri writes: > = > >> FWIW, the for S-IMSIC the write is already writel(), so we'll have the > >> text patching and IPI ordered. Regardless, there's more than one flavor > >> of IPI on RISC-V! > > > > AFAIU, this writel() is intended to order the insertion (and the initia= lization) > > of the CSD object before the MMIO writes; so, the "right fix" seems to = turn the > > "other flavors" into using a writel() or providing a similar ordering g= uarantee. > = > Yes, that's probably the right approach, or maybe follow-up! > = > > As a bonus, such change should address/fix all current and future occur= rences of > > the message-passing scenario in question (the patch addressed the occur= rence in > > flush_icache_all(), but there appears to be a similar one in flush_icac= he_mm()). > = > Indeed. I wonder if the SBI remote fence.i needs it? Ah! So I am not alone: AFAICT, that remains a matter of discussions with y= our SEE team/developers. :-| Andrea _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CE362627EC for ; Tue, 11 Mar 2025 18:11:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741716678; cv=none; b=O+uIF3oFX7x9/Hep1iwqam3j+/CwELMTltujVs/ejH5IuvvDK1UlKiOnJLhHUiAaIGzUv/02r+5vsKYTSqrcMPFCYw/jYbcjLEuG7W9PuGAzAXYKZTDaqFQVh8kaabMewlGFyj0PkZfMxwkO/u/t9qh/kFtnLHlYUzefXvtkSSM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 11 Mar 2025 11:11:14 -0700 (PDT) Received: from andrea ([31.189.82.201]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac2929390b4sm453700066b.75.2025.03.11.11.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 11:11:14 -0700 (PDT) Date: Tue, 11 Mar 2025 19:11:10 +0100 From: Andrea Parri To: =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Cc: Andy Chiu , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, bjorn@rivosinc.com, puranjay12@gmail.com, alexghiti@rivosinc.com, yongxuan.wang@sifive.com, greentime.hu@sifive.com, nick.hu@sifive.com, nylon.chen@sifive.com, tommy.wu@sifive.com, eric.lin@sifive.com, viccent.chen@sifive.com, zong.li@sifive.com, samuel.holland@sifive.com Subject: Re: [PATCH v3 6/7] riscv: add a data fence for CMODX in the kernel mode Message-ID: References: <20241127172908.17149-1-andybnac@gmail.com> <20241127172908.17149-7-andybnac@gmail.com> <87ldtck8k0.fsf@all.your.base.are.belong.to.us> <87ldtbwrdb.fsf@all.your.base.are.belong.to.us> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87ldtbwrdb.fsf@all.your.base.are.belong.to.us> On Tue, Mar 11, 2025 at 03:53:36PM +0100, Björn Töpel wrote: > Andrea Parri writes: > > >> FWIW, the for S-IMSIC the write is already writel(), so we'll have the > >> text patching and IPI ordered. Regardless, there's more than one flavor > >> of IPI on RISC-V! > > > > AFAIU, this writel() is intended to order the insertion (and the initialization) > > of the CSD object before the MMIO writes; so, the "right fix" seems to turn the > > "other flavors" into using a writel() or providing a similar ordering guarantee. > > Yes, that's probably the right approach, or maybe follow-up! > > > As a bonus, such change should address/fix all current and future occurrences of > > the message-passing scenario in question (the patch addressed the occurrence in > > flush_icache_all(), but there appears to be a similar one in flush_icache_mm()). > > Indeed. I wonder if the SBI remote fence.i needs it? Ah! So I am not alone: AFAICT, that remains a matter of discussions with your SEE team/developers. :-| Andrea