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Wed, 12 Mar 2025 12:39:27 -0400 X-MC-Unique: ILaNx7quPZ6PLyUsjPAsQw-1 X-Mimecast-MFC-AGG-ID: ILaNx7quPZ6PLyUsjPAsQw_1741797565 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 2A18319560B2; Wed, 12 Mar 2025 16:39:24 +0000 (UTC) Received: from redhat.com (unknown [10.42.28.57]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id DAA9A19560AD; Wed, 12 Mar 2025 16:39:17 +0000 (UTC) Date: Wed, 12 Mar 2025 16:39:14 +0000 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Shameerali Kolothum Thodi Cc: "eric.auger@redhat.com" , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "ddutile@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb-pcie bus Message-ID: References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-6-shameerali.kolothum.thodi@huawei.com> <79bcc36c-1a12-4b18-a54c-afe734d6bef0@redhat.com> <9ffee8119fc441aeb760073c5f152fa4@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9ffee8119fc441aeb760073c5f152fa4@huawei.com> User-Agent: Mutt/2.2.13 (2024-03-09) X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass client-ip=170.10.129.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: ZHgp40RVZWCk On Wed, Mar 12, 2025 at 04:34:18PM +0000, Shameerali Kolothum Thodi wrote: > Hi Eric, > > > -----Original Message----- > > From: Eric Auger > > Sent: Wednesday, March 12, 2025 4:08 PM > > To: Shameerali Kolothum Thodi > > ; qemu-arm@nongnu.org; > > qemu-devel@nongnu.org > > Cc: peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com; > > ddutile@redhat.com; berrange@redhat.com; nathanc@nvidia.com; > > mochs@nvidia.com; smostafa@google.com; Linuxarm > > ; Wangzhou (B) ; > > jiangkunkun ; Jonathan Cameron > > ; zhangfei.gao@linaro.org > > Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb- > > pcie bus > > > > Hi Shameer, > > > > > > On 3/11/25 3:10 PM, Shameer Kolothum wrote: > > > User must associate a pxb-pcie root bus to smmuv3-accel > > > and that is set as the primary-bus for the smmu dev. > > why do we require a pxb-pcie root bus? why can't pci.0 root bus be used > > for simpler use cases (ie. I just want to passthough a NIC in > > accelerated mode). Or may pci.0 is also called a pax-pcie root bus? > > The idea was since pcie.0 is the default RC with virt, leave that to cases where > we want to attach any emulated devices and use pxb-pcie based RCs for vfio-pci. The majority of management applications will never do anything other than a flat PCI(e) topology by default. Some might enable pxb-pcie as an optional but plenty won't ever support it. If you want to maximise the potential usefulness of the ssmmuv3-accel, and it is technically viable, it would be worth permitting choice of attachment to the root bus as an alteranative to the pxb. With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|