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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Alejandro Vallejo <alejandro.vallejo@cloud.com>
Cc: Stewart Hildebrand <stewart.hildebrand@amd.com>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] [RFC] vpci: allow BAR write while mapped
Date: Thu, 13 Mar 2025 18:58:35 +0100	[thread overview]
Message-ID: <Z9Mcy9j8ec-TjipY@macbook.local> (raw)
In-Reply-To: <D8F8IW559J11.2G40MDQH23I44@cloud.com>

On Thu, Mar 13, 2025 at 03:14:26PM +0000, Alejandro Vallejo wrote:
> On Wed Mar 12, 2025 at 7:50 PM GMT, Stewart Hildebrand wrote:
> > Xen vPCI refuses BAR writes if the BAR is mapped in p2m. If firmware
> > initialized the BAR to a bad address, Linux will try to write a new
> > address to the BAR without disabling memory decoding. Allow the write
> > by updating p2m right away in the vPCI BAR write handler.
> >
> > Resolves: https://gitlab.com/xen-project/xen/-/issues/197
> > Signed-off-by: Stewart Hildebrand <stewart.hildebrand@amd.com>
> > ---
> > RFC: Currently the deferred mapping machinery supports only map or
> >      unmap, not both. It might be better to rework the mapping machinery
> >      to support unmap-then-map operations, but please let me know your
> >      thoughts.
> > RFC: This patch has not yet made an attempt to distinguish between
> >      32-bit and 64-bit writes. It probably should.
> > ---
> >  xen/drivers/vpci/header.c | 65 +++++++++++++++++++++++++++++++--------
> >  1 file changed, 53 insertions(+), 12 deletions(-)
> >
> > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
> > index ef6c965c081c..66adb2183cfe 100644
> > --- a/xen/drivers/vpci/header.c
> > +++ b/xen/drivers/vpci/header.c
> > @@ -173,7 +173,7 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd,
> >          ASSERT_UNREACHABLE();
> >  }
> >  
> > -bool vpci_process_pending(struct vcpu *v)
> > +static bool process_pending(struct vcpu *v, bool need_lock)
> >  {
> >      struct pci_dev *pdev = v->vpci.pdev;
> >      struct vpci_header *header = NULL;
> > @@ -182,12 +182,14 @@ bool vpci_process_pending(struct vcpu *v)
> >      if ( !pdev )
> >          return false;
> >  
> > -    read_lock(&v->domain->pci_lock);
> > +    if ( need_lock )
> > +        read_lock(&v->domain->pci_lock);
> >  
> >      if ( !pdev->vpci || (v->domain != pdev->domain) )
> >      {
> >          v->vpci.pdev = NULL;
> > -        read_unlock(&v->domain->pci_lock);
> > +        if ( need_lock )
> > +            read_unlock(&v->domain->pci_lock);
> >          return false;
> >      }
> >  
> > @@ -209,17 +211,20 @@ bool vpci_process_pending(struct vcpu *v)
> >  
> >          if ( rc == -ERESTART )
> >          {
> > -            read_unlock(&v->domain->pci_lock);
> > +            if ( need_lock )
> > +                read_unlock(&v->domain->pci_lock);
> >              return true;
> >          }
> >  
> >          if ( rc )
> >          {
> > -            spin_lock(&pdev->vpci->lock);
> > +            if ( need_lock )
> > +                spin_lock(&pdev->vpci->lock);
> >              /* Disable memory decoding unconditionally on failure. */
> >              modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY,
> >                              false);
> > -            spin_unlock(&pdev->vpci->lock);
> > +            if ( need_lock )
> > +                spin_unlock(&pdev->vpci->lock);
> >  
> >              /* Clean all the rangesets */
> >              for ( i = 0; i < ARRAY_SIZE(header->bars); i++ )
> > @@ -228,7 +233,8 @@ bool vpci_process_pending(struct vcpu *v)
> >  
> >              v->vpci.pdev = NULL;
> >  
> > -            read_unlock(&v->domain->pci_lock);
> > +            if ( need_lock )
> > +                read_unlock(&v->domain->pci_lock);
> >  
> >              if ( !is_hardware_domain(v->domain) )
> >                  domain_crash(v->domain);
> > @@ -238,15 +244,23 @@ bool vpci_process_pending(struct vcpu *v)
> >      }
> >      v->vpci.pdev = NULL;
> >  
> > -    spin_lock(&pdev->vpci->lock);
> > +    if ( need_lock )
> > +        spin_lock(&pdev->vpci->lock);
> >      modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only);
> > -    spin_unlock(&pdev->vpci->lock);
> > +    if ( need_lock )
> > +        spin_unlock(&pdev->vpci->lock);
> >  
> > -    read_unlock(&v->domain->pci_lock);
> > +    if ( need_lock )
> > +        read_unlock(&v->domain->pci_lock);
> >  
> >      return false;
> >  }
> >  
> > +bool vpci_process_pending(struct vcpu *v)
> > +{
> > +    return process_pending(v, true);
> > +}
> > +
> >  static int __init apply_map(struct domain *d, const struct pci_dev *pdev,
> >                              uint16_t cmd)
> >  {
> > @@ -565,6 +579,8 @@ static void cf_check bar_write(
> >  {
> >      struct vpci_bar *bar = data;
> >      bool hi = false;
> > +    bool reenable = false;
> > +    uint32_t cmd = 0;
> >  
> >      ASSERT(is_hardware_domain(pdev->domain));
> >  
> > @@ -585,10 +601,31 @@ static void cf_check bar_write(
> >      {
> >          /* If the value written is the current one avoid printing a warning. */
> >          if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) )
> > +        {
> >              gprintk(XENLOG_WARNING,
> > -                    "%pp: ignored BAR %zu write while mapped\n",
> > +                    "%pp: allowing BAR %zu write while mapped\n",
> >                      &pdev->sbdf, bar - pdev->vpci->header.bars + hi);
> > -        return;
> > +            ASSERT(rw_is_write_locked(&pdev->domain->pci_lock));
> > +            ASSERT(spin_is_locked(&pdev->vpci->lock));
> > +            reenable = true;
> > +            cmd = pci_conf_read16(pdev->sbdf, PCI_COMMAND);
> > +            /*
> > +             * Write-while-mapped: unmap the old BAR in p2m. We want this to
> > +             * finish right away since the deferral machinery only supports
> > +             * unmap OR map, not unmap-then-remap. Ultimately, it probably would
> > +             * be better to defer the write-while-mapped case just like regular
> > +             * BAR writes (but still only allow it for 32-bit BAR writes).
> > +             */
> > +            /* Disable memory decoding */
> > +            modify_bars(pdev, cmd & ~PCI_COMMAND_MEMORY, false);
> > +            /* Call process pending here to ensure P2M operations are done */
> > +            while ( process_pending(current, false) )
> > +            {
> > +                /* Pre-empted, try again */
> 
> This seems a tad dangerous. There may be a non-negligible amount of work queued
> up. I also wonder whether the guest can induce spinning by increasing
> contention on the p2m (e.g: via ballooning) or by induces work being queued up.
> 
> I don't quite understand the logic, but I suspect you could
> raise_softirq(SCHEDULE_SOFTIRQ), decrease the IP so the instruction is
> replayed, release the locks, and simply exit the hypervisor.

There's no instruction replay in this case, instead the vCPU is
prevented from resuming operation until the deferred pending operation
is finished.  This is done by preventing hvm_do_resume() from
succeeding as long as vpci_process_pending() return true.

> The system ought
> to naturally split the operation in several continuations each of which does
> either unmapping or mapping if it couldn't be done in a single one. Replaying
> the instruction after decoding is disabled ought to be benign.

IMO the main issue is how to signal which operations are pending, so
they can be executed in the deferred context.  `struct vpci_vcpu` is
used to hold a single pending operation.

> I haven't tried any of what I just wrote, so take it with with several tons of
> salt though.
> 
> Do you know if Linux intentionally skips disabling decode? Or is it a bug?

For 32bit BARs it's possible to atomically reposition them with a
single atomic write, so Linux will try to do that.  For 64bit BARs
this is not possible (as it involves writes to two registers), and
hence Linux won't usually attempt to atomically reposition 64bit BARs.

Thanks, Roger.


  parent reply	other threads:[~2025-03-13 17:59 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-12 19:50 [PATCH] [RFC] vpci: allow BAR write while mapped Stewart Hildebrand
2025-03-13 15:14 ` Alejandro Vallejo
2025-03-13 17:43   ` Stewart Hildebrand
2025-03-14 10:39     ` Alejandro Vallejo
2025-03-17 12:32       ` Roger Pau Monné
2025-03-17 13:49         ` Alejandro Vallejo
2025-03-13 17:58   ` Roger Pau Monné [this message]
2025-03-13 17:48 ` Roger Pau Monné
2025-03-13 18:28   ` Stewart Hildebrand
2025-03-14  8:04   ` Jan Beulich
2025-03-14  8:21     ` Roger Pau Monné
2025-03-14  8:26       ` Jan Beulich

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