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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="YiN+E6HlXMbGwqPo" Content-Disposition: inline In-Reply-To: <20250318082945.52019-1-roger.pau@citrix.com> --YiN+E6HlXMbGwqPo Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Tue, 18 Mar 2025 12:23:24 +0100 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Roger Pau Monne Cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper Subject: Re: [PATCH] x86/msi: always propagate MSI writes when not in active system mode On Tue, Mar 18, 2025 at 09:29:45AM +0100, Roger Pau Monne wrote: > Relax the limitation on MSI register writes, and only apply it when the > system is in active state. For example AMD IOMMU drivers rely on using > set_msi_affinity() to force an MSI register write on resume from > suspension. >=20 > The original patch intention was to reduce the number of MSI register > writes when the system is in active state. Leave the other states to > always perform the writes, as it's safer given the existing code, and it's > expected to not make a difference performance wise. >=20 > For such propagation to work even when the IRT index is not updated the M= SI > message must be adjusted in all success cases for AMD IOMMU, not just when > the index has been newly allocated. >=20 > Reported-by: Marek Marczykowski-G=C3=B3recki > Fixes: ('8e60d47cf011 x86/iommu: avoid MSI address and data writes if IRT= index hasn't changed') > Signed-off-by: Roger Pau Monn=C3=A9 Tested-by: Marek Marczykowski-G=C3=B3recki > --- > xen/arch/x86/msi.c | 9 +++++++++ > xen/drivers/passthrough/amd/iommu_intr.c | 2 +- > 2 files changed, 10 insertions(+), 1 deletion(-) >=20 > diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c > index 163ccf874720..8bb3bb18af61 100644 > --- a/xen/arch/x86/msi.c > +++ b/xen/arch/x86/msi.c > @@ -189,6 +189,15 @@ static int write_msi_msg(struct msi_desc *entry, str= uct msi_msg *msg, > { > entry->msg =3D *msg; > =20 > + if ( unlikely(system_state !=3D SYS_STATE_active) ) > + /* > + * Always propagate writes when not in the 'active' state. The > + * optimization to avoid the MSI address and data registers writ= e is > + * only relevant for runtime state, and drivers on resume (at le= ast) > + * rely on set_msi_affinity() to update the hardware state. > + */ > + force =3D true; > + > if ( iommu_intremap !=3D iommu_intremap_off ) > { > int rc; > diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passt= hrough/amd/iommu_intr.c > index 9abdc38053d7..08766122b421 100644 > --- a/xen/drivers/passthrough/amd/iommu_intr.c > +++ b/xen/drivers/passthrough/amd/iommu_intr.c > @@ -546,7 +546,7 @@ int cf_check amd_iommu_msi_msg_update_ire( > rc =3D update_intremap_entry_from_msi_msg(iommu, bdf, nr, > &msi_desc->remap_index, > msg, &data); > - if ( rc > 0 ) > + if ( rc >=3D 0 ) > { > for ( i =3D 1; i < nr; ++i ) > msi_desc[i].remap_index =3D msi_desc->remap_index + i; > --=20 > 2.48.1 >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --YiN+E6HlXMbGwqPo Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmfZV6wACgkQ24/THMrX 1yyxwwf+IwXgGNJJvhYAl8e0zEHnG3+vG7ZI/aodha8fi7mp5GSo0oiLkpt6xQrL Ytr+hC3DAo8zhTSKChER0RGYDZyvOv68HYiVf98V9TQsphmVFJeNKSj+OHJpvTPy 7I082IAt87zcUBz5LOg6155y22LTy3aXqyqxd0v0vcP8drWKBit6MX0BgyGzJzoA yIkApTJ+XYeUZAOtMA7buZ8tHxvFoKQe7VOZrxkbmyIVM+Gltn4BeEr2xV2ImArs tCoFgNC09sscjvM8h66b+1jOGm+ObwTDsoE8JQhzjQxXVuIZor0o4ENCob54u2lS 6BjZYOa3XibYmYqselOwrcylPTt0xA== =5qL6 -----END PGP SIGNATURE----- --YiN+E6HlXMbGwqPo--