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[34.87.152.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c68a8775sm107397615ad.95.2025.03.19.00.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 00:43:10 -0700 (PDT) Date: Wed, 19 Mar 2025 07:43:03 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Daniel Mentz , iommu@lists.linux.dev Subject: Re: [RFC PATCH 1/5] iommu/arm-smmu-v3: Refactor arm_smmu_setup_irqs Message-ID: References: <20250319004254.2547950-1-praan@google.com> <20250319004254.2547950-2-praan@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Mar 18, 2025 at 09:50:16PM -0700, Nicolin Chen wrote: > On Wed, Mar 19, 2025 at 12:42:50AM +0000, Pranjal Shrivastava wrote: > > Refactor arm_smmu_setup_irqs by splitting it into two parts, one for > > registering interrupt handlers and the other one for enabling interrupt > > generation in the hardware. This refactor helps in re-initialization of > > hardware interrupts as part of a subsequent patch that enables runtime > > power management for the arm-smmu-v3 driver. > > > > Signed-off-by: Pranjal Shrivastava > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 50 ++++++++++++++++----- > > 1 file changed, 38 insertions(+), 12 deletions(-) > > > +static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) > > +{ > > + int ret, irq; > > + > > + /* Disable IRQs first */ > > + ret = arm_smmu_disable_irqs(smmu); > > Why do we need to touch HW in this SW handler setting-up function? > This is just to maintain status quo, if you look at the current `arm_smmu_setup_irqs` we still: /* Disable IRQs first */ ret = arm_smmu_write_reg_sync(smmu, 0,ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); > > @@ -4171,6 +4187,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > > return ret; > > } > > > > + /* Enable interrupt generation on the SMMU */ > > + arm_smmu_enable_irqs(smmu); > > + > > Should this replace arm_smmu_setup_irqs() in this function? I see > arm_smmu_setup_irqs() still remain in arm_smmu_device_reset(), so > a normal probe routine would call it twice? > > In my view, arm_smmu_setup_irqs() can be done just once, moving > out of arm_smmu_device_reset() and up to arm_smmu_device_probe()? > That makes sense, I kept the `arm_smmu_setup_irqs()` here to re-init the MSIs during resume but I guess it's better to call `arm_smmu_setup_irqs` once during probe and maybe re-work to call `arm_smmu_setup_msis` during resume to re-alloc the MSIs. I'll add this in the next version. Thanks, Praan