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Tue, 18 Mar 2025 21:50:17 -0700 Date: Tue, 18 Mar 2025 21:50:16 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: Joerg Roedel , Will Deacon , "Robin Murphy" , Jason Gunthorpe , Mostafa Saleh , Daniel Mentz , Subject: Re: [RFC PATCH 1/5] iommu/arm-smmu-v3: Refactor arm_smmu_setup_irqs Message-ID: References: <20250319004254.2547950-1-praan@google.com> <20250319004254.2547950-2-praan@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250319004254.2547950-2-praan@google.com> X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34C:EE_|DS7PR12MB9551:EE_ X-MS-Office365-Filtering-Correlation-Id: 2bd1d2ac-b1c4-4bf8-e034-08dd66a193f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024|7053199007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2025 04:50:31.3360 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2bd1d2ac-b1c4-4bf8-e034-08dd66a193f5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9551 On Wed, Mar 19, 2025 at 12:42:50AM +0000, Pranjal Shrivastava wrote: > Refactor arm_smmu_setup_irqs by splitting it into two parts, one for > registering interrupt handlers and the other one for enabling interrupt > generation in the hardware. This refactor helps in re-initialization of > hardware interrupts as part of a subsequent patch that enables runtime > power management for the arm-smmu-v3 driver. > > Signed-off-by: Pranjal Shrivastava > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 50 ++++++++++++++++----- > 1 file changed, 38 insertions(+), 12 deletions(-) > +static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) > +{ > + int ret, irq; > + > + /* Disable IRQs first */ > + ret = arm_smmu_disable_irqs(smmu); Why do we need to touch HW in this SW handler setting-up function? > @@ -4171,6 +4187,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > return ret; > } > > + /* Enable interrupt generation on the SMMU */ > + arm_smmu_enable_irqs(smmu); > + Should this replace arm_smmu_setup_irqs() in this function? I see arm_smmu_setup_irqs() still remain in arm_smmu_device_reset(), so a normal probe routine would call it twice? In my view, arm_smmu_setup_irqs() can be done just once, moving out of arm_smmu_device_reset() and up to arm_smmu_device_probe()? Thanks Nicolin