From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 01/29] x86: treewide: Introduce x86_vendor_amd_or_hygon()
Date: Thu, 20 Mar 2025 11:47:00 +0100 [thread overview]
Message-ID: <Z9vyJLXNL2-CTIIG@lx-t490> (raw)
In-Reply-To: <14F10A4B-A274-40B2-9609-669E09981812@zytor.com>
On Wed, 19 Mar 2025, H. Peter Anvin wrote:
>
> On March 18, "Ahmed S. Darwish" wrote:
> >
> > Then I found that there are 28 other cases in the x86 tree where the
> > AMD/Hygon CPU vendor check is also combined. So I did that macro and
> > it also made a number the affected sites more succinct; e.g.:
> >
> > ...
>
> I would agree that abstracting this into something higher level makes
> sense, but have you considered whether or not it is actually necessary
> to do this in the first place? In the case of level 0x8000001d for
> example, that should be handled by the end bracket from leaf
> 0x80000000.
>
> In general, VFMS checks are not a good thing.
>
Great point, I'll consider that when I (soon) touch these areas again.
In the next PQ, wherea cached CPUID table built on early boot, "CPUID
truth" is centralized. This way, the VMFS checks can indeed be reduced.
Thanks!
--
Ahmed S. Darwish
Linutronix GmbH
next prev parent reply other threads:[~2025-03-20 10:47 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-17 16:47 [PATCH v2 00/29] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 01/29] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-17 17:32 ` Borislav Petkov
2025-03-17 17:48 ` Peter Zijlstra
2025-03-17 18:10 ` Andrew Cooper
2025-03-17 18:34 ` H. Peter Anvin
2025-03-17 18:11 ` Dave Hansen
2025-03-17 18:21 ` H. Peter Anvin
2025-03-17 18:34 ` Borislav Petkov
2025-03-18 11:07 ` Ahmed S. Darwish
2025-03-19 14:47 ` H. Peter Anvin
2025-03-20 10:47 ` Ahmed S. Darwish [this message]
2025-03-17 21:42 ` Ingo Molnar
2025-03-17 21:46 ` Borislav Petkov
2025-03-17 16:47 ` [PATCH v2 02/29] x86/cpuid: Refactor <asm/cpuid.h> Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 03/29] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-17 21:36 ` Ingo Molnar
2025-03-18 11:09 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 04/29] x86/cacheinfo: Use CPUID leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 05/29] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 06/29] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 07/29] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 08/29] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 09/29] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 10/29] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 11/29] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 12/29] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 13/29] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 14/29] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 15/29] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 16/29] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 17/29] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 18/29] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-19 14:11 ` kernel test robot
2025-03-19 16:09 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 19/29] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-19 16:09 ` kernel test robot
2025-03-19 16:16 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 20/29] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 21/29] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 22/29] x86/cpu: " Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 23/29] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 24/29] x86/cacheinfo: Separate Intel leaf 0x4 handling Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 25/29] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 26/29] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 27/29] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 28/29] x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 29/29] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z9vyJLXNL2-CTIIG@lx-t490 \
--to=darwi@linutronix.de \
--cc=andrew.cooper3@citrix.com \
--cc=bp@alien8.de \
--cc=dave.hansen@linux.intel.com \
--cc=hpa@zytor.com \
--cc=john.ogness@linutronix.de \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=tglx@linutronix.de \
--cc=x86-cpuid@lists.linux.dev \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.