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Thu, 20 Mar 2025 09:47:33 -0700 Date: Thu, 20 Mar 2025 09:47:32 -0700 From: Nicolin Chen To: Yi Liu CC: , , , , , , , , , Subject: Re: [PATCH v8 4/5] iommufd: Extend IOMMU_GET_HW_INFO to report PASID capability Message-ID: References: <20250313124753.185090-1-yi.l.liu@intel.com> <20250313124753.185090-5-yi.l.liu@intel.com> <444284f3-2dae-4aa9-a897-78a36e1be3ca@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <444284f3-2dae-4aa9-a897-78a36e1be3ca@intel.com> X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F63:EE_|SJ0PR12MB6685:EE_ X-MS-Office365-Filtering-Correlation-Id: 222190e1-ac1a-4278-6bfb-08dd67ceef5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2025 16:47:43.2145 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 222190e1-ac1a-4278-6bfb-08dd67ceef5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6685 On Thu, Mar 20, 2025 at 08:48:49PM +0800, Yi Liu wrote: > On 2025/3/20 01:58, Nicolin Chen wrote: > > On Thu, Mar 13, 2025 at 05:47:52AM -0700, Yi Liu wrote: > > > PASID usage requires PASID support in both device and IOMMU. Since the > > > iommu drivers always enable the PASID capability for the device if it > > > is supported, this extends the IOMMU_GET_HW_INFO to report the PASID > > > capability to userspace. Also, enhances the selftest accordingly. > > > > Overall, I am a bit confused by the out_capabilities field in the > > IOMMU_GET_HW_INFO. Why these capabilities cannot be reported via > > the driver specific data structure? > > > > E.g. we don't report the "NESTING" capability in out_capabilities > > at all and that works fine since the iommu driver would reject if > > it doesn't support. > > NESTING is a bit different. Userspace needs to know underlying PASID > cap and further expose it to guest if it wants. While NESTING is not > from this angle. It's just for the use of userspace. So a try and fail > is ok. Hmm, would you please elaborate the difference more? Also, what's that "further expose"? > > Mind elaborate the reason for these two new capabilities? What is > > the benefit from keeping them in the core v.s. driver level? > > I view the PASID cap is generic just like the DIRTY_TRACKING cap. Well, I actually don't get the DIRTY_TRACKING cap either. Based on what I see from Zhenzhong's implementation in the QEMU, it totally could be a vendor-specific cap: we can just add another PCIIOMMUOps op for QEMU core to ask the IOMMU device model to get hw_info and allocate a DIRTY_TRACKING-enabled HWPT to return that to the core, instead of core detecting the out_capabilities in the common path. In that regard, honestly, I don't quite get this out_capabilities. > Reporting them in the driver-specific part is fine, but I doubt > if it is better since PASID cap is generic to all vendors. The argument could be that NESTING is generic to all vendors too, yet we don't have that in out_capabilities :-/ Thanks Nicolin