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Tue, 14 Mar 2023 07:28:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230253AbjCNH2D (ORCPT ); Tue, 14 Mar 2023 03:28:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229573AbjCNH2A (ORCPT ); Tue, 14 Mar 2023 03:28:00 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF8F319C68 for ; Tue, 14 Mar 2023 00:27:56 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 32E7R5Us098208; Tue, 14 Mar 2023 15:27:05 +0800 (+08) (envelope-from dylan@andestech.com) Received: from APC323 (10.0.12.101) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 14 Mar 2023 15:27:04 +0800 Date: Tue, 14 Mar 2023 15:27:28 +0800 From: Dylan Jhong To: Zong Li CC: , , , , , , , , , , , Subject: Re: [PATCH v2] riscv: mm: Fix incorrect ASID argument when flushing TLB Message-ID: References: <20230313034906.2401730-1-dylan@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-Originating-IP: [10.0.12.101] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 32E7R5Us098208 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 14, 2023 at 10:22:43AM +0800, Zong Li wrote: > Dylan Jhong 於 2023年3月13日 週一 下午12:29寫道： > > > > Currently, we pass the CONTEXTID instead of the ASID to the TLB flush > > function. We should only take the ASID field to prevent from touching > > the reserved bit field. > > > > Fixes: 3f1e782998cd ("riscv: add ASID-based tlbflushing methods") > > Signed-off-by: Dylan Jhong > > --- > > Hi Dylan, > Thanks for your patch, if I remember correctly, there was a patch from > Alistair Francis did the similar fix. Perhaps we should track that > patch to see why it doesn't be merged. Thanks. > > http://lists.infradead.org/pipermail/linux-riscv/2022-March/013558.html > Hi Zong, Thanks for the reminder, I didn't notice that Alistair had sent the same patch before. Hi Palmer, Alistair http://lists.infradead.org/pipermail/linux-riscv/2022-March/013597.html This patch does not seem to be cherry-picked back to the released linux kernel, and I have not seen the v4 patch. May I ask how is the follow-up progress of this patch? Best, Dylan > > Changes from v2: > > - Remove unsued EXPORT_SYMBOL() > > --- > > arch/riscv/include/asm/tlbflush.h | 2 ++ > > arch/riscv/mm/context.c | 2 +- > > arch/riscv/mm/tlbflush.c | 2 +- > > 3 files changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > > index 907b9efd39a8..597d6d8aec28 100644 > > --- a/arch/riscv/include/asm/tlbflush.h > > +++ b/arch/riscv/include/asm/tlbflush.h > > @@ -12,6 +12,8 @@ > > #include > > > > #ifdef CONFIG_MMU > > +extern unsigned long asid_mask; > > + > > static inline void local_flush_tlb_all(void) > > { > > __asm__ __volatile__ ("sfence.vma" : : : "memory"); > > diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c > > index 80ce9caba8d2..6d1aeb063e81 100644 > > --- a/arch/riscv/mm/context.c > > +++ b/arch/riscv/mm/context.c > > @@ -22,7 +22,7 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); > > > > static unsigned long asid_bits; > > static unsigned long num_asids; > > -static unsigned long asid_mask; > > +unsigned long asid_mask; > > > > static atomic_long_t current_version; > > > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > > index ce7dfc81bb3f..ba4c27187c95 100644 > > --- a/arch/riscv/mm/tlbflush.c > > +++ b/arch/riscv/mm/tlbflush.c > > @@ -27,7 +27,7 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, > > /* check if the tlbflush needs to be sent to other CPUs */ > > broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > > if (static_branch_unlikely(&use_asid_allocator)) { > > - unsigned long asid = atomic_long_read(&mm->context.id); > > + unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask; > > > > /* > > * TLB will be immediately flushed on harts concurrently > > -- > > 2.34.1 > >