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From: Mostafa Saleh <smostafa@google.com>
To: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org, jean-philippe@linaro.org,
	peter.maydell@linaro.org, qemu-arm@nongnu.org,
	richard.henderson@linaro.org
Subject: Re: [RFC PATCH v2 03/11] hw/arm/smmuv3: Refactor stage-1 PTW
Date: Sun, 19 Mar 2023 08:38:24 +0000	[thread overview]
Message-ID: <ZBbKAPs6xFHNKw37@google.com> (raw)
In-Reply-To: <13459f92-da9f-f7a8-9c18-1870a9def7e8@redhat.com>

Hi Eric,

On Fri, Mar 17, 2023 at 07:31:06PM +0100, Eric Auger wrote:
> > +#define SMMU_LEVELS                         4
> > +
> > +#define SMMU_STRIDE(gran)                   ((gran) - SMMU_LEVELS + 1)
> > +#define SMMU_BIT_LVL(isz, strd, lvl)        ((isz) - (strd) * \
> > +                                             (SMMU_LEVELS - (lvl)))
> > +#define SMMU_IDXMSK(isz, strd, lvl)         ((1ULL << \
> > +                                             SMMU_BIT_LVL(isz, strd, lvl)) - 1)
> This looks good to me. Just a question about the BIT_LVL and IDXMSK
> defines. Do they correspond to any documented pseudocode functions
> documented somewhere in the ARM ARM?

I see they are not implemented as functions in ARM ARM, but as part of
aarch64/translation/vmsa_addrcalc/AArch64.TTBaseAddress:
	constant integer FINAL_LEVEL = 3;
	levels = FINAL_LEVEL - startlevel;
	tsize = (iasize - (levels*stride + granulebits)) + 3;
	tablebase = Align(tablebase, 1 << tsize);

This gives the same result, however the equations are a bit different as
they use final level(3), while we use number of levels(4).


Thanks,
Mostafa

  reply	other threads:[~2023-03-19  8:39 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-26 22:06 [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 01/11] hw/arm/smmuv3: Add missing fields for IDR0 Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 02/11] hw/arm/smmuv3: Update translation config to hold stage-2 Mostafa Saleh
2023-03-17 11:37   ` Eric Auger
2023-03-17 14:43     ` Mostafa Saleh
2023-03-17 17:36       ` Eric Auger
2023-02-26 22:06 ` [RFC PATCH v2 03/11] hw/arm/smmuv3: Refactor stage-1 PTW Mostafa Saleh
2023-03-17 18:31   ` Eric Auger
2023-03-19  8:38     ` Mostafa Saleh [this message]
2023-02-26 22:06 ` [RFC PATCH v2 04/11] hw/arm/smmuv3: Add page table walk for stage-2 Mostafa Saleh
2023-03-20 14:56   ` Eric Auger
2023-03-20 18:52     ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 05/11] hw/arm/smmuv3: Parse STE config " Mostafa Saleh
2023-03-20 15:14   ` Eric Auger
2023-03-20 19:11     ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 06/11] hw/arm/smmuv3: Make TLB lookup work " Mostafa Saleh
2023-03-20 16:05   ` Eric Auger
2023-03-20 19:14     ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 07/11] hw/arm/smmuv3: Add VMID to tlb tagging Mostafa Saleh
2023-03-20 16:16   ` Eric Auger
2023-02-26 22:06 ` [RFC PATCH v2 08/11] hw/arm/smmuv3: Add CMDs related to stage-2 Mostafa Saleh
2023-03-20 16:51   ` Eric Auger
2023-03-20 19:29     ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 09/11] hw/arm/smmuv3: Add stage-2 support in iova notifier Mostafa Saleh
2023-03-20 16:57   ` Eric Auger
2023-02-26 22:06 ` [RFC PATCH v2 10/11] hw/arm/smmuv3: Populate OAS based on CPU PARANGE Mostafa Saleh
2023-03-20 17:12   ` Eric Auger
2023-03-21 13:06     ` Mostafa Saleh
2023-03-21 13:23       ` Eric Auger
2023-03-21 13:29         ` Mostafa Saleh
2023-03-21 13:34           ` Eric Auger
2023-03-21 13:34         ` Peter Maydell
2023-03-21 13:42           ` Mostafa Saleh
2023-03-21 13:45           ` Eric Auger
2023-03-21 13:54           ` Mostafa Saleh
2023-03-21 14:08             ` Peter Maydell
2023-02-26 22:06 ` [RFC PATCH v2 11/11] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 Mostafa Saleh

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