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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="DPxcdv3g2IgGGUVa" Content-Disposition: inline In-Reply-To: <540906f7-4543-9d01-2b2b-a3bd70eda74b@suse.com> --DPxcdv3g2IgGGUVa Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Tue, 28 Mar 2023 14:52:42 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel@lists.xenproject.org, Jason Andryuk , Andrew Cooper , Wei Liu , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: [PATCH v2 2/3] x86/hvm: Allow writes to registers on the same page as MSI-X table On Tue, Mar 28, 2023 at 02:34:23PM +0200, Jan Beulich wrote: > On 28.03.2023 14:05, Marek Marczykowski-G=C3=B3recki wrote: > > On Tue, Mar 28, 2023 at 01:28:44PM +0200, Roger Pau Monn=C3=A9 wrote: > >> On Sat, Mar 25, 2023 at 03:49:23AM +0100, Marek Marczykowski-G=C3=B3re= cki wrote: > >>> +static bool cf_check msixtbl_page_accept( > >>> + const struct hvm_io_handler *handler, const ioreq_t *r) > >>> +{ > >>> + ASSERT(r->type =3D=3D IOREQ_TYPE_COPY); > >>> + > >>> + return msixtbl_page_handler_get_hwaddr( > >>> + current->domain, r->addr, r->dir =3D=3D IOREQ_WRITE); > >> > >> I think you want to accept it also if it's a write to the PBA, and > >> just drop it. You should always pass write=3Dfalse and then drop it in > >> msixtbl_page_write() if it falls in the PBA region (but still return > >> X86EMUL_OKAY). > >=20 > > I don't want to interfere with msixtbl_mmio_page_ops, this handler is > > only about accesses not hitting actual MSI-X structures. >=20 > In his functionally similar vPCI change I did ask Roger to handle the > "extra" space right from the same handlers. Maybe that's going to be > best here, too. I have considered this option, but msixtbl_range() is already quite complex, adding yet another case there won't make it easier to follow. I mean, technically I can probably merge those two handlers together, but I don't think it will result in nicer code. Especially since the general direction is to abandon split of MSI-X table access handling between Xen and QEMU and go with just QEMU doing it, hopefully at some point not needing msixtbl_mmio_ops anymore (but still needing the one for adjacent accesses). > >>> --- a/xen/arch/x86/msi.c > >>> +++ b/xen/arch/x86/msi.c > >>> @@ -961,6 +961,34 @@ static int msix_capability_init(struct pci_dev *= dev, > >>> domain_crash(d); > >>> /* XXX How to deal with existing mappings? */ > >>> } > >>> + > >>> + /* > >>> + * If the MSI-X table doesn't start at the page boundary, ma= p the first page for > >>> + * passthrough accesses. > >>> + */ > >> > >> I think you should initialize > >> msix->adj_access_table_idx[ADJ_IDX_{FIRST,LAST}] to -1? >=20 > Or better not use a signed type there and set to UINT_MAX here. If not using 0 as unused entry (see the other commend I made in response to Roger), then that's probably the way to go. --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --DPxcdv3g2IgGGUVa Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmQi4xoACgkQ24/THMrX 1yzvKAf8CTEChxywfyFBs4MSJLFYlMwM4zkOdi/Gf3bsDgvSjAiUSejvNFGPqJaf ThQjMa8wEH1/QXiHRDvOYIYDWyIMn77HVYyMTtnodlwZefxgWQzsIcoD2/WcVerG AyH8m3skeny2lV+SHwTTdvqMQaPmDTM9+CdKs2cOlgIAjoDDe+mCov4cR3P6+4lf j8AeCkGLltigN6tWsxwsGlCgI2zcE8eIqHBTiDwsurdUubDPqCAoYv8ZJ/TL8uGp qFSGA8kfDG8cq87VU7cisbu6szrvLnN4GoZFCX+OiDutc4VhUrdQNDfLZs6hmCK+ 1UFN6Sn3OJbnhK2V61d4SZqFimb3Hg== =60Jc -----END PGP SIGNATURE----- --DPxcdv3g2IgGGUVa--