From: Gregory Price <gregory.price@memverge.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org, Dave Jiang <dave.jiang@intel.com>
Subject: Re: [PATCH] cxl/hdm: Extend DVSEC range register emulation for region enumeration
Date: Wed, 29 Mar 2023 13:21:11 -0400 [thread overview]
Message-ID: <ZCRzh0VLSVF/7jya@memverge.com> (raw)
In-Reply-To: <64250e45bea49_c722294c2@dwillia2-mobl3.amr.corp.intel.com.notmuch>
On Wed, Mar 29, 2023 at 09:21:25PM -0700, Dan Williams wrote:
> > Is the DVSEC Range Register expected to be programmed by bios, and are
> > not being programmed correctly?
>
> This debug experiment makes me think perhaps the *device* is at fault,
> not the BIOS. Perhaps the device accepts writes to CXL_DVSEC_RANGE_BASE
> to set up the decode as expected, but reads return 0? That's the only
> way that I can see that forcing that offset results in successfully
> talking to memory.
>
Oh, i meant to add that i tested whether the memory is accessible via
numactl --membind=1 with both memhog and a python prompt, and things
worked just fine. So memory works.
next prev parent reply other threads:[~2023-03-30 4:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-29 21:35 [PATCH] cxl/hdm: Extend DVSEC range register emulation for region enumeration Dan Williams
2023-03-29 16:04 ` Gregory Price
2023-03-30 4:21 ` Dan Williams
2023-03-29 17:20 ` Gregory Price
2023-05-16 6:43 ` Gregory Price
2023-03-29 17:21 ` Gregory Price [this message]
2023-03-30 6:33 ` Dan Williams
2023-03-30 4:27 ` Gregory Price
2023-04-16 4:05 ` Gregory Price
2023-04-18 5:51 ` Dan Williams
2023-04-20 0:50 ` Gregory Price
2023-03-30 0:06 ` Dave Jiang
2023-03-30 17:00 ` Jonathan Cameron
2023-03-30 18:24 ` Dan Williams
2023-04-03 23:06 ` [PATCH v2] " Dan Williams
2023-04-03 23:44 ` Dave Jiang
2023-04-04 0:08 ` Dan Williams
2023-04-04 0:16 ` Dave Jiang
2023-04-04 9:19 ` Jonathan Cameron
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