From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Christopherson Date: Thu, 20 Apr 2023 13:21:28 -0700 Subject: [RFC 00/48] RISC-V CoVE support In-Reply-To: References: <20230419221716.3603068-1-atishp@rivosinc.com> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Fri, Apr 21, 2023, Atish Kumar Patra wrote: > On Thu, Apr 20, 2023 at 10:00?PM Sean Christopherson wrote: > > > > On Wed, Apr 19, 2023, Atish Patra wrote: > > > 2. Lazy gstage page allocation vs upfront allocation with page pool. > > > Currently, all gstage mappings happen at runtime during the fault. This is expensive > > > as we need to convert that page to confidential memory as well. A page pool framework > > > may be a better choice which can hold all the confidential pages which can be > > > pre-allocated upfront. A generic page pool infrastructure may benefit other CC solutions ? > > > > I'm sorry, what? Do y'all really not pay any attention to what is happening > > outside of the RISC-V world? > > > > We, where "we" is KVM x86 and ARM, with folks contributing from 5+ companines, > > have been working on this problem for going on three *years*. And that's just > > from the first public posting[1], there have been discussions about how to approach > > this for even longer. There have been multiple related presentations at KVM Forum, > > something like 4 or 5 just at KVM Forum 2022 alone. > > > > I did mention about that in the 1st item in the TODO list. My apologies, I completely missed the todo list. > Thanks for your suggestion. It seems we should just directly move to > restrictedmem asap. Yes please, for the sake of everyone involved. It will likely save you from running into the same pitfalls that x86 and ARM already encountered, and the more eyeballs and use cases on whatever restrictemem ends up being called, the better. Thanks! From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E92059445 for ; Thu, 20 Apr 2023 20:21:30 +0000 (UTC) Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2476a718feeso1186931a91.2 for ; Thu, 20 Apr 2023 13:21:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682022090; x=1684614090; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=mpTOoqFwr6PXx8ZhPhp2F5vKR6FTzxj9fbkenjMTw+I=; b=ayMsf68dO1AJVJrABTkUhl1NMkj9wzJIuYm23qPHqGOJfv8Tzmr/MMZxooBdbFWuv6 cTmzvZGQL22AByne/8vqNIb7Ula7gng50G2+VKpqMx484CV6DQsedQ06XTaeu+DQM49b Xv9bZenL7yQF4ga4/MTIH59v2WCdxiBmdnXbayZvn5qNdcPSs6tpTkKYHX2oOZ/dvVZJ 7iBN8GopMbKfBq0gxr0rs7bCE35mGMrwZMp+IWcuRhn8r0n6FUEqG0/jssdTgwXjPBGo QXUjX+PVWO6OKOdititLEBWM39bjy4BtfGL6XjtBawa9+EgUy4H8fBEsjKUgS+1l2k/k uAwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682022090; x=1684614090; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=mpTOoqFwr6PXx8ZhPhp2F5vKR6FTzxj9fbkenjMTw+I=; b=Sd8tOsAQMaTILWb8+EgtiI+vxUUxVCrRY6jmFXibCDWaPrQc8GXzFKuADtpQrjskll l7e0lY4bR6QZIBlyrS2/RuPTHX6xvZeiik7BJeApe0Zuk6siJhWnQ4a78R+nDeull/vT HZQJEzKbsATLGe8UN/HPoGo5dH3l26uasFl/AZoknnDMTqVQ+VA4DPMfjj0dGOXxCJN/ qNx4IrJs1pzOb8/1rYwTYjFbvDbLcbRNH5SzzTaXrD0XVqs+UZ0/7Et1+9rNZS549irc T/t3i3cZk69Cwvq8igVRkI5pn3S/5q5F4FWCkNk3bgb812NVUFwKcJO5GEm3v61iCPGr H+rw== X-Gm-Message-State: AAQBX9cUevLNwjW2uZLCZ5/4e+tT+9EDbj0+jYSd9lFIQHcaFRRU64gQ 1HxTA8TywL34MrdzxqVn9lU+L6J5saI= X-Google-Smtp-Source: AKy350bOw0CcGSD5HxBsCHP7eQv+pVq4+ffvtFW6Bs0RrLmmQY0i686r1Bx3KLV/2OwqstA5HB5kaL3ma/k= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90a:470b:b0:247:e66:1d90 with SMTP id h11-20020a17090a470b00b002470e661d90mr728232pjg.6.1682022090286; Thu, 20 Apr 2023 13:21:30 -0700 (PDT) Date: Thu, 20 Apr 2023 13:21:28 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20230419221716.3603068-1-atishp@rivosinc.com> Message-ID: Subject: Re: [RFC 00/48] RISC-V CoVE support From: Sean Christopherson To: Atish Kumar Patra Cc: linux-kernel@vger.kernel.org, Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , "=?iso-8859-1?Q?Bj=F6rn_T=F6pel?=" , Suzuki K Poulose , Will Deacon , Marc Zyngier , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Rajnesh Kanwal , Uladzislau Rezki Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Fri, Apr 21, 2023, Atish Kumar Patra wrote: > On Thu, Apr 20, 2023 at 10:00=E2=80=AFPM Sean Christopherson wrote: > > > > On Wed, Apr 19, 2023, Atish Patra wrote: > > > 2. Lazy gstage page allocation vs upfront allocation with page pool. > > > Currently, all gstage mappings happen at runtime during the fault. Th= is is expensive > > > as we need to convert that page to confidential memory as well. A pag= e pool framework > > > may be a better choice which can hold all the confidential pages whic= h can be > > > pre-allocated upfront. A generic page pool infrastructure may benefit= other CC solutions ? > > > > I'm sorry, what? Do y'all really not pay any attention to what is happ= ening > > outside of the RISC-V world? > > > > We, where "we" is KVM x86 and ARM, with folks contributing from 5+ comp= anines, > > have been working on this problem for going on three *years*. And that= 's just > > from the first public posting[1], there have been discussions about how= to approach > > this for even longer. There have been multiple related presentations a= t KVM Forum, > > something like 4 or 5 just at KVM Forum 2022 alone. > > >=20 > I did mention about that in the 1st item in the TODO list. My apologies, I completely missed the todo list. > Thanks for your suggestion. It seems we should just directly move to > restrictedmem asap. Yes please, for the sake of everyone involved. It will likely save you fro= m running into the same pitfalls that x86 and ARM already encountered, and th= e more eyeballs and use cases on whatever restrictemem ends up being called, the b= etter. Thanks! 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Thu, 20 Apr 2023 13:21:30 -0700 (PDT) Date: Thu, 20 Apr 2023 13:21:28 -0700 In-Reply-To: Mime-Version: 1.0 References: <20230419221716.3603068-1-atishp@rivosinc.com> Message-ID: Subject: Re: [RFC 00/48] RISC-V CoVE support From: Sean Christopherson To: Atish Kumar Patra Cc: linux-kernel@vger.kernel.org, Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , "=?iso-8859-1?Q?Bj=F6rn_T=F6pel?=" , Suzuki K Poulose , Will Deacon , Marc Zyngier , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Rajnesh Kanwal , Uladzislau Rezki X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230420_132131_851675_27CB8569 X-CRM114-Status: GOOD ( 20.90 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gRnJpLCBBcHIgMjEsIDIwMjMsIEF0aXNoIEt1bWFyIFBhdHJhIHdyb3RlOgo+IE9uIFRodSwg QXByIDIwLCAyMDIzIGF0IDEwOjAw4oCvUE0gU2VhbiBDaHJpc3RvcGhlcnNvbiA8c2VhbmpjQGdv b2dsZS5jb20+IHdyb3RlOgo+ID4KPiA+IE9uIFdlZCwgQXByIDE5LCAyMDIzLCBBdGlzaCBQYXRy YSB3cm90ZToKPiA+ID4gMi4gTGF6eSBnc3RhZ2UgcGFnZSBhbGxvY2F0aW9uIHZzIHVwZnJvbnQg YWxsb2NhdGlvbiB3aXRoIHBhZ2UgcG9vbC4KPiA+ID4gQ3VycmVudGx5LCBhbGwgZ3N0YWdlIG1h cHBpbmdzIGhhcHBlbiBhdCBydW50aW1lIGR1cmluZyB0aGUgZmF1bHQuIFRoaXMgaXMgZXhwZW5z aXZlCj4gPiA+IGFzIHdlIG5lZWQgdG8gY29udmVydCB0aGF0IHBhZ2UgdG8gY29uZmlkZW50aWFs IG1lbW9yeSBhcyB3ZWxsLiBBIHBhZ2UgcG9vbCBmcmFtZXdvcmsKPiA+ID4gbWF5IGJlIGEgYmV0 dGVyIGNob2ljZSB3aGljaCBjYW4gaG9sZCBhbGwgdGhlIGNvbmZpZGVudGlhbCBwYWdlcyB3aGlj aCBjYW4gYmUKPiA+ID4gcHJlLWFsbG9jYXRlZCB1cGZyb250LiBBIGdlbmVyaWMgcGFnZSBwb29s IGluZnJhc3RydWN0dXJlIG1heSBiZW5lZml0IG90aGVyIENDIHNvbHV0aW9ucyA/Cj4gPgo+ID4g SSdtIHNvcnJ5LCB3aGF0PyAgRG8geSdhbGwgcmVhbGx5IG5vdCBwYXkgYW55IGF0dGVudGlvbiB0 byB3aGF0IGlzIGhhcHBlbmluZwo+ID4gb3V0c2lkZSBvZiB0aGUgUklTQy1WIHdvcmxkPwo+ID4K PiA+IFdlLCB3aGVyZSAid2UiIGlzIEtWTSB4ODYgYW5kIEFSTSwgd2l0aCBmb2xrcyBjb250cmli dXRpbmcgZnJvbSA1KyBjb21wYW5pbmVzLAo+ID4gaGF2ZSBiZWVuIHdvcmtpbmcgb24gdGhpcyBw cm9ibGVtIGZvciBnb2luZyBvbiB0aHJlZSAqeWVhcnMqLiAgQW5kIHRoYXQncyBqdXN0Cj4gPiBm cm9tIHRoZSBmaXJzdCBwdWJsaWMgcG9zdGluZ1sxXSwgdGhlcmUgaGF2ZSBiZWVuIGRpc2N1c3Np b25zIGFib3V0IGhvdyB0byBhcHByb2FjaAo+ID4gdGhpcyBmb3IgZXZlbiBsb25nZXIuICBUaGVy ZSBoYXZlIGJlZW4gbXVsdGlwbGUgcmVsYXRlZCBwcmVzZW50YXRpb25zIGF0IEtWTSBGb3J1bSwK PiA+IHNvbWV0aGluZyBsaWtlIDQgb3IgNSBqdXN0IGF0IEtWTSBGb3J1bSAyMDIyIGFsb25lLgo+ ID4KPiAKPiBJIGRpZCBtZW50aW9uIGFib3V0IHRoYXQgaW4gdGhlIDFzdCBpdGVtIGluIHRoZSBU T0RPIGxpc3QuCgpNeSBhcG9sb2dpZXMsIEkgY29tcGxldGVseSBtaXNzZWQgdGhlIHRvZG8gbGlz dC4KCj4gVGhhbmtzIGZvciB5b3VyIHN1Z2dlc3Rpb24uIEl0IHNlZW1zIHdlIHNob3VsZCBqdXN0 IGRpcmVjdGx5IG1vdmUgdG8KPiByZXN0cmljdGVkbWVtIGFzYXAuCgpZZXMgcGxlYXNlLCBmb3Ig dGhlIHNha2Ugb2YgZXZlcnlvbmUgaW52b2x2ZWQuICBJdCB3aWxsIGxpa2VseSBzYXZlIHlvdSBm cm9tCnJ1bm5pbmcgaW50byB0aGUgc2FtZSBwaXRmYWxscyB0aGF0IHg4NiBhbmQgQVJNIGFscmVh ZHkgZW5jb3VudGVyZWQsIGFuZCB0aGUgbW9yZQpleWViYWxscyBhbmQgdXNlIGNhc2VzIG9uIHdo YXRldmVyIHJlc3RyaWN0ZW1lbSBlbmRzIHVwIGJlaW5nIGNhbGxlZCwgdGhlIGJldHRlci4KClRo YW5rcyEKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxp bnV4LXJpc2N2IG1haWxpbmcgbGlzdApsaW51eC1yaXNjdkBsaXN0cy5pbmZyYWRlYWQub3JnCmh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcmlzY3YK