From: Piotr Raczynski <piotr.raczynski@intel.com>
To: "alexis.lothore@bootlin.com" <alexis.lothore@bootlin.com>
Cc: "andrew@lunn.ch" <andrew@lunn.ch>,
"f.fainelli@gmail.com" <f.fainelli@gmail.com>,
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"kuba@kernel.org" <kuba@kernel.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
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Subject: Re: [PATCH net v3 1/3] net: dsa: rzn1-a5psw: enable management frames for CPU port
Date: Fri, 12 May 2023 16:20:15 +0200 [thread overview]
Message-ID: <ZF5LH91XDIh9ArfG@nimitz> (raw)
In-Reply-To: <20230512072712.82694-2-alexis.lothore@bootlin.com>
On Fri, May 12, 2023 at 09:27:10AM +0200, alexis.lothore@bootlin.com wrote:
> From: Clément Léger <clement.leger@bootlin.com>
>
> Currently, management frame were discarded before reaching the CPU port due
> to a misconfiguration of the MGMT_CONFIG register. Enable them by setting
> the correct value in this register in order to correctly receive management
> frame and handle STP.
>
> Fixes: 888cdb892b61 ("net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver")
> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
> Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
> ---
> Changes since v2:
> - move A5PSW_MGMT_CFG_ENABLE definition in this commit
> ---
Looks OK, thanks.
Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com>
next prev parent reply other threads:[~2023-05-12 14:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 7:27 [PATCH net v3 0/3] net: dsa: rzn1-a5psw: fix STP states handling alexis.lothore
2023-05-12 7:27 ` [PATCH net v3 1/3] net: dsa: rzn1-a5psw: enable management frames for CPU port alexis.lothore
2023-05-12 14:20 ` Piotr Raczynski [this message]
2023-05-12 7:27 ` [PATCH net v3 2/3] net: dsa: rzn1-a5psw: fix STP states handling alexis.lothore
2023-05-12 7:27 ` [PATCH net v3 3/3] net: dsa: rzn1-a5psw: disable learning for standalone ports alexis.lothore
2023-05-12 15:43 ` Piotr Raczynski
2023-05-13 16:30 ` [PATCH net v3 0/3] net: dsa: rzn1-a5psw: fix STP states handling patchwork-bot+netdevbpf
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