From: Oliver Upton <oliver.upton@linux.dev>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Ricardo Koller <ricarkol@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Jing Zhang <jingzhangos@google.com>,
Colton Lewis <coltonlewis@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 7/7] KVM: arm64: Use TLBI range-based intructions for unmap
Date: Fri, 12 May 2023 17:02:38 +0000 [thread overview]
Message-ID: <ZF5xLrr2tEYdLL1i@linux.dev> (raw)
In-Reply-To: <20230414172922.812640-8-rananta@google.com>
Hi Raghavendra,
On Fri, Apr 14, 2023 at 05:29:22PM +0000, Raghavendra Rao Ananta wrote:
> The current implementation of the stage-2 unmap walker traverses
> the given range and, as a part of break-before-make, performs
> TLB invalidations with a DSB for every PTE. A multitude of this
> combination could cause a performance bottleneck.
>
> Hence, if the system supports FEAT_TLBIRANGE, defer the TLB
> invalidations until the entire walk is finished, and then
> use range-based instructions to invalidate the TLBs in one go.
> Condition this upon S2FWB in order to avoid walking the page-table
> again to perform the CMOs after issuing the TLBI.
>
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> Suggested-by: Oliver Upton <oliver.upton@linux.dev>
> ---
> arch/arm64/kvm/hyp/pgtable.c | 33 +++++++++++++++++++++++++++++----
> 1 file changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
> index 3f136e35feb5e..bcb748e3566c7 100644
> --- a/arch/arm64/kvm/hyp/pgtable.c
> +++ b/arch/arm64/kvm/hyp/pgtable.c
> @@ -987,10 +987,16 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtable *pgt, u64 addr, u64 size,
> return ret;
> }
>
> +struct stage2_unmap_data {
> + struct kvm_pgtable *pgt;
> + bool skip_pte_tlbis;
> +};
> +
> static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx,
> enum kvm_pgtable_walk_flags visit)
> {
> - struct kvm_pgtable *pgt = ctx->arg;
> + struct stage2_unmap_data *unmap_data = ctx->arg;
> + struct kvm_pgtable *pgt = unmap_data->pgt;
> struct kvm_s2_mmu *mmu = pgt->mmu;
> struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops;
> kvm_pte_t *childp = NULL;
> @@ -1018,7 +1024,7 @@ static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx,
> * block entry and rely on the remaining portions being faulted
> * back lazily.
> */
> - stage2_put_pte(ctx, mmu, mm_ops, false);
> + stage2_put_pte(ctx, mmu, mm_ops, unmap_data->skip_pte_tlbis);
>
> if (need_flush && mm_ops->dcache_clean_inval_poc)
> mm_ops->dcache_clean_inval_poc(kvm_pte_follow(ctx->old, mm_ops),
> @@ -1032,13 +1038,32 @@ static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx,
>
> int kvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 addr, u64 size)
> {
> + int ret;
> + struct stage2_unmap_data unmap_data = {
> + .pgt = pgt,
> + /*
> + * If FEAT_TLBIRANGE is implemented, defer the individial PTE
> + * TLB invalidations until the entire walk is finished, and
> + * then use the range-based TLBI instructions to do the
> + * invalidations. Condition this upon S2FWB in order to avoid
> + * a page-table walk again to perform the CMOs after TLBI.
> + */
> + .skip_pte_tlbis = system_supports_tlb_range() &&
> + stage2_has_fwb(pgt),
Why can't the underlying walker just call these two helpers directly?
There are static keys behind these...
> + };
> struct kvm_pgtable_walker walker = {
> .cb = stage2_unmap_walker,
> - .arg = pgt,
> + .arg = &unmap_data,
> .flags = KVM_PGTABLE_WALK_LEAF | KVM_PGTABLE_WALK_TABLE_POST,
> };
>
> - return kvm_pgtable_walk(pgt, addr, size, &walker);
> + ret = kvm_pgtable_walk(pgt, addr, size, &walker);
> + if (unmap_data.skip_pte_tlbis)
> + /* Perform the deferred TLB invalidations */
> + kvm_call_hyp(__kvm_tlb_flush_vmid_range, pgt->mmu,
> + addr, addr + size);
> +
> + return ret;
> }
>
> struct stage2_attr_data {
> --
> 2.40.0.634.g4ca3ef3211-goog
>
--
Thanks,
Oliver
next prev parent reply other threads:[~2023-05-12 17:02 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-14 17:29 [PATCH v3 0/7] KVM: arm64: Add support for FEAT_TLBIRANGE Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-04-14 17:29 ` [PATCH v3 1/7] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-04-17 16:17 ` Catalin Marinas
2023-04-17 16:17 ` Catalin Marinas
2023-04-14 17:29 ` [PATCH v3 2/7] KVM: arm64: Implement __kvm_tlb_flush_vmid_range() Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-05-12 16:50 ` Oliver Upton
2023-05-16 17:17 ` Raghavendra Rao Ananta
2023-05-16 17:17 ` Raghavendra Rao Ananta
2023-04-14 17:29 ` [PATCH v3 3/7] KVM: arm64: Implement kvm_arch_flush_remote_tlbs_range() Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-04-14 17:29 ` [PATCH v3 4/7] KVM: arm64: Flush only the memslot after write-protect Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-04-14 17:29 ` [PATCH v3 5/7] KVM: arm64: Invalidate the table entries upon a range Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-04-14 17:29 ` [PATCH v3 6/7] KVM: arm64: Add 'skip_flush' arg to stage2_put_pte() Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-05-12 17:21 ` Oliver Upton
2023-05-16 17:32 ` Raghavendra Rao Ananta
2023-05-16 17:32 ` Raghavendra Rao Ananta
2023-04-14 17:29 ` [PATCH v3 7/7] KVM: arm64: Use TLBI range-based intructions for unmap Raghavendra Rao Ananta
2023-04-14 17:29 ` Raghavendra Rao Ananta
2023-05-12 17:02 ` Oliver Upton [this message]
2023-05-16 17:21 ` Raghavendra Rao Ananta
2023-05-16 17:21 ` Raghavendra Rao Ananta
2023-05-16 18:46 ` Oliver Upton
2023-05-16 18:46 ` Oliver Upton
2023-05-16 18:54 ` Raghavendra Rao Ananta
2023-05-16 18:54 ` Raghavendra Rao Ananta
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