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s=k20201202; t=1683562845; bh=hNKbhjXj4sq7siJDAnA0CwKqmHnlz6fdow6mqG667FA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=vC/3ScToQKhedFLfxUFSJ3aCnIFQ0ilNTcZmOvWfnMTfly0Y9+O7vzM0QHX8Y06eC c7fRRlONd+f2NO7xa8jTaXN8agDMHkEG8a4KmDON8G0osb5Jw5TwquFB8n360h6lfd BpC7Hi39UPl1zzmAVZ77ZoVtKVB+17cKZLXXIjjkC+zQvGKcv4oOFR1pxeku74nVFS 7XkdKiTUMB59g96XuAhNv9sDvb9ckYlFLNH8M/FOw3VLSMZh8Mm/IVuasrRHULRqS9 /48L1lKQrFX8SbG3gt16Mv5iEMzBQsWJ+3vdWEi3JbSXSSco99OeSo8rpK0PXtNp/P LVmby35lajZAw== Date: Tue, 9 May 2023 00:09:38 +0800 From: Jisheng Zhang To: Guo Ren Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Message-ID: References: <20230507182304.2934-1-jszhang@kernel.org> <20230507182304.2934-2-jszhang@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, May 08, 2023 at 02:52:29PM +0800, Guo Ren wrote: > On Mon, May 8, 2023 at 2:34 AM Jisheng Zhang wrote: > > > > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > > access from S-mode, but it doesn't need the edge quirk. > > > > Signed-off-by: Jisheng Zhang > > --- > > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > > drivers/irqchip/irq-sifive-plic.c | 1 + > > 2 files changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > index f75736a061af..64b43a3c3748 100644 > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > @@ -62,6 +62,10 @@ properties: > > - starfive,jh7110-plic > > - canaan,k210-plic > > - const: sifive,plic-1.0.0 > > + - items: > > + - enum: > > + - thead,light-plic > > + - const: thead,c910-plic > > - items: > > - enum: > > - allwinner,sun20i-d1-plic > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index e1484905b7bd..71afa2a584d9 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, > > } > > > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > > +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); > > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ > > > > static int __init plic_edge_init(struct device_node *node, > > -- > > 2.40.0 > > > opensbi needs thead,c900-plic, and we could put multi compatible name > in the dts. So, it's no need here. Thanks, I misunderstood the PLIC edge quirk. This patch isn't needed any more.