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From: Oliver Upton To: Mark Brown Cc: Catalin Marinas , Will Deacon , Marc Zyngier , James Morse , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, Shaoqin Huang Subject: Re: [PATCH v2 2/7] arm64/sysreg: Convert MDSCR_EL1 to automatic register generation Message-ID: References: <20230419-arm64-syreg-gen-v2-0-4c6add1f6257@kernel.org> <20230419-arm64-syreg-gen-v2-2-4c6add1f6257@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230419-arm64-syreg-gen-v2-2-4c6add1f6257@kernel.org> X-Migadu-Flow: FLOW_OUT On Tue, May 23, 2023 at 07:37:00PM +0100, Mark Brown wrote: > Convert MDSCR_EL1 to automatic register generation as per DDI0616 2023-03. > No functional change. > > Reviewed-by: Shaoqin Huang > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/sysreg.h | 1 - > arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ > 2 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 3d69bda0e608..95de1aaee0e9 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -135,7 +135,6 @@ > #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) > > #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) > -#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) > #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) > #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) > #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index df7a7ba97b43..601cc8024734 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -55,6 +55,34 @@ Field 29 TX > Res0 28:0 > EndSysreg > > +Sysreg MDSCR_EL1 2 0 0 2 2 > +Res0 63:36 > +Field 35 EHBWE > +Field 34 EnSPM > +Field 33 TTA > +Field 32 EMBWE > +Field 31 TFO > +Field 30 RXfull > +Field 29 TXfull > +Res0 28 > +Field 27 RXO > +Field 26 TXU > +Res0 25:24 > +Field 23:22 INTdis > +Field 21 TDA > +Res0 20 > +Field 19 SC2 > +Res0 18:16 These bits are actually RAZ/WI. I know that doesn't amount to much right now, but eventually getting a mask of RAZ/WI bits for registers would be helpful for KVM sysreg emulation. > +Field 15 MDE > +Field 14 HDE > +Field 13 KDE > +Field 12 TDCC > +Res0 11:7 > +Field 6 ERR > +Res0 5:1 > +Field 0 SS > +EndSysreg > + > Sysreg ID_PFR0_EL1 3 0 0 1 0 > Res0 63:32 > UnsignedEnum 31:28 RAS > > -- > 2.30.2 > -- Thanks, Oliver From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41115C77B7E for ; Thu, 25 May 2023 21:39:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xefeo9QezvkGqP1AwvZZlLlaDTVRus+cIaHcp9P7dkI=; b=H7eKVPnzqpVFiD 64heqJKoKgHmjTBrsccqOeb5EqCVhpwji2y7akE5IjfdCwjPsxaIO4cp1mgKCKBRpc6ffF7MrAegB yQ9NsNwX5+XMOYgEmBrwykTe3wxQkQAfsA4N9ZkaNP3V0MFX32p7xuUNEim/EfKJ8kwVHiEcznJqt qI4HgIAc4Scf52t8jDOt+jfa/ycSkrXYvM7fq7EhfRqB5Nb3GjFaom8D/f6qXzGs8IzJG/aFrP1bx 8BPzYLaKN/X6bFnLToWH711tSqbvHo8vT7nDebjy65EqpQacy2dxofA+UTw7QNANhzxKPyTW2PglX KMa1fQZBFbZj8YQwgkGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2Ig8-000DjM-1r; Thu, 25 May 2023 21:39:24 +0000 Received: from out-46.mta1.migadu.com ([2001:41d0:203:375::2e]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2Ig4-000DiS-3D for linux-arm-kernel@lists.infradead.org; Thu, 25 May 2023 21:39:22 +0000 Date: Thu, 25 May 2023 21:39:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1685050757; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=9+VwLV0iEPlynwi1LSTqGxgNADCv+g+kF4twYCaw1HI=; b=Hh/9PSeJIJyO2wP2Dx8GQ2aYt07ldwJNuqorWUj9m6abnDMvq0iJX4oM6iadR/GfTLFlYg Vgc7aLrOCotbyRiXeASo+Towwwl42xyDagWgrOEUrsA1SIbG7BmPBrUf5SBOTMoyQElNHB KuiZno9COc9Nehu73qxC4VqQ1lIvDp4= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Mark Brown Cc: Catalin Marinas , Will Deacon , Marc Zyngier , James Morse , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, Shaoqin Huang Subject: Re: [PATCH v2 2/7] arm64/sysreg: Convert MDSCR_EL1 to automatic register generation Message-ID: References: <20230419-arm64-syreg-gen-v2-0-4c6add1f6257@kernel.org> <20230419-arm64-syreg-gen-v2-2-4c6add1f6257@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230419-arm64-syreg-gen-v2-2-4c6add1f6257@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230525_143921_430194_0C886078 X-CRM114-Status: GOOD ( 14.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 23, 2023 at 07:37:00PM +0100, Mark Brown wrote: > Convert MDSCR_EL1 to automatic register generation as per DDI0616 2023-03. > No functional change. > > Reviewed-by: Shaoqin Huang > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/sysreg.h | 1 - > arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ > 2 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 3d69bda0e608..95de1aaee0e9 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -135,7 +135,6 @@ > #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) > > #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) > -#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) > #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) > #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) > #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index df7a7ba97b43..601cc8024734 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -55,6 +55,34 @@ Field 29 TX > Res0 28:0 > EndSysreg > > +Sysreg MDSCR_EL1 2 0 0 2 2 > +Res0 63:36 > +Field 35 EHBWE > +Field 34 EnSPM > +Field 33 TTA > +Field 32 EMBWE > +Field 31 TFO > +Field 30 RXfull > +Field 29 TXfull > +Res0 28 > +Field 27 RXO > +Field 26 TXU > +Res0 25:24 > +Field 23:22 INTdis > +Field 21 TDA > +Res0 20 > +Field 19 SC2 > +Res0 18:16 These bits are actually RAZ/WI. I know that doesn't amount to much right now, but eventually getting a mask of RAZ/WI bits for registers would be helpful for KVM sysreg emulation. > +Field 15 MDE > +Field 14 HDE > +Field 13 KDE > +Field 12 TDCC > +Res0 11:7 > +Field 6 ERR > +Res0 5:1 > +Field 0 SS > +EndSysreg > + > Sysreg ID_PFR0_EL1 3 0 0 1 0 > Res0 63:32 > UnsignedEnum 31:28 RAS > > -- > 2.30.2 > -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel