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From: Bjorn Helgaas <helgaas@kernel.org>
To: Terry Bowman <terry.bowman@amd.com>
Cc: alison.schofield@intel.com, vishal.l.verma@intel.com,
	ira.weiny@intel.com, bwidawsk@kernel.org,
	dan.j.williams@intel.com, dave.jiang@intel.com,
	Jonathan.Cameron@huawei.com, linux-cxl@vger.kernel.org,
	rrichter@amd.com, linux-kernel@vger.kernel.org,
	bhelgaas@google.com, Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
	Oliver O'Halloran <oohall@gmail.com>,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 18/23] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
Date: Wed, 24 May 2023 11:55:18 -0500	[thread overview]
Message-ID: <ZG5BdvAP1OuQVTWz@bhelgaas> (raw)
In-Reply-To: <20230523232214.55282-19-terry.bowman@amd.com>

On Tue, May 23, 2023 at 06:22:09PM -0500, Terry Bowman wrote:
> The CXL driver plans to use cper_print_aer() for logging restricted CXL
> host (RCH) AER errors. cper_print_aer() is not currently exported and
> therefore not usable by the CXL driver built as a loadable module. Export
> the cper_print_aer() function making it available.
> 
> The CONFIG_ACPI_APEI_PCIEAER kernel config is currently used to enable
> cper_print_aer(). cper_print_aer() logs the AER registers and is
> useful in PCIE AER logging outside of APEI. Remove the
> CONFIG_ACPI_APEI_PCIEAER dependency to enable cper_print_aer().
> 
> The cper_print_aer() function name implies CPER specific use but is useful
> in non-CPER cases as well. Rename cper_print_aer() to pci_print_aer().
> 
> Co-developed-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: "Oliver O'Halloran" <oohall@gmail.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci@vger.kernel.org
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
>  drivers/pci/pcie/aer.c | 9 +++++----
>  include/linux/aer.h    | 2 +-
>  2 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index f6c24ded134c..d3344fcf1f79 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -771,9 +771,10 @@ int cper_severity_to_aer(int cper_severity)
>  	}
>  }
>  EXPORT_SYMBOL_GPL(cper_severity_to_aer);
> +#endif
>  
> -void cper_print_aer(struct pci_dev *dev, int aer_severity,
> -		    struct aer_capability_regs *aer)
> +void pci_print_aer(struct pci_dev *dev, int aer_severity,
> +		   struct aer_capability_regs *aer)
>  {
>  	int layer, agent, tlp_header_valid = 0;
>  	u32 status, mask;
> @@ -812,7 +813,7 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity,
>  	trace_aer_event(dev_name(&dev->dev), (status & ~mask),
>  			aer_severity, tlp_header_valid, &aer->header_log);
>  }
> -#endif
> +EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL);
>  
>  /**
>   * add_error_device - list device to be handled
> @@ -1009,7 +1010,7 @@ static void aer_recover_work_func(struct work_struct *work)
>  			       PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
>  			continue;
>  		}
> -		cper_print_aer(pdev, entry.severity, entry.regs);
> +		pci_print_aer(pdev, entry.severity, entry.regs);
>  		if (entry.severity == AER_NONFATAL)
>  			pcie_do_recovery(pdev, pci_channel_io_normal,
>  					 aer_root_reset);
> diff --git a/include/linux/aer.h b/include/linux/aer.h
> index 97f64ba1b34a..8f124b904314 100644
> --- a/include/linux/aer.h
> +++ b/include/linux/aer.h
> @@ -64,7 +64,7 @@ static inline void pci_save_aer_state(struct pci_dev *dev) {}
>  static inline void pci_restore_aer_state(struct pci_dev *dev) {}
>  #endif
>  
> -void cper_print_aer(struct pci_dev *dev, int aer_severity,
> +void pci_print_aer(struct pci_dev *dev, int aer_severity,
>  		    struct aer_capability_regs *aer);
>  int cper_severity_to_aer(int cper_severity);
>  void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
> -- 
> 2.34.1
> 

  reply	other threads:[~2023-05-24 16:55 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-23 23:21 [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-05-23 23:21 ` [PATCH v4 01/23] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-01 10:13   ` Jonathan Cameron
2023-06-02 14:16     ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 02/23] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-01 10:38   ` Jonathan Cameron
2023-06-02 14:53     ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 03/23] cxl: Rename member @dport of struct cxl_dport to @dev Terry Bowman
2023-06-01 10:41   ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 04/23] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-01 10:49   ` Jonathan Cameron
2023-06-02 15:11     ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 05/23] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-01 10:52   ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 06/23] cxl/acpi: Moving add_host_bridge_uport() around Terry Bowman
2023-06-01 10:54   ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 07/23] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-01 12:45   ` Jonathan Cameron
2023-06-02 15:42     ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 08/23] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-01 12:49   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 09/23] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-01 12:59   ` Jonathan Cameron
2023-06-02 15:45     ` Robert Richter
2023-05-23 23:22 ` [PATCH v4 10/23] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-01 13:06   ` Jonathan Cameron
2023-06-02 15:58     ` Robert Richter
2023-05-23 23:22 ` [PATCH v4 11/23] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-01 13:07   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 12/23] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-01 13:07   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 13/23] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-05-24  1:12   ` kernel test robot
2023-05-24  9:49     ` Robert Richter
2023-05-25 20:23   ` kernel test robot
2023-06-01 13:11   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 14/23] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-01 13:27   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 15/23] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-01 13:28   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 16/23] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-01 13:28   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 17/23] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-01 13:36   ` Jonathan Cameron
2023-06-01 13:38   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 18/23] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-05-24 16:55   ` Bjorn Helgaas [this message]
2023-05-25 21:38     ` Terry Bowman
2023-05-23 23:22 ` [PATCH v4 19/23] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-01 13:42   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 20/23] cxl/pci: Prepare for logging RCH downstream port protocol errors Terry Bowman
2023-06-01 13:49   ` Jonathan Cameron
2023-06-01 14:06     ` Terry Bowman
2023-06-01 14:12       ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 21/23] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-01 14:03   ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 22/23] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-05-23 23:22   ` Terry Bowman
2023-05-24 21:32   ` Bjorn Helgaas
2023-05-24 21:32     ` Bjorn Helgaas
2023-05-25 21:29     ` Robert Richter
2023-05-25 21:29       ` Robert Richter
2023-05-25 22:01       ` Bjorn Helgaas
2023-05-25 22:01         ` Bjorn Helgaas
2023-05-25 22:28         ` Robert Richter
2023-05-25 22:28           ` Robert Richter
2023-06-01 14:06   ` Jonathan Cameron
2023-06-01 14:06     ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 23/23] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-05-24 21:45   ` Bjorn Helgaas
2023-05-25 22:08     ` Robert Richter
2023-05-26 20:31       ` Bjorn Helgaas
2023-06-01 14:11         ` Jonathan Cameron
2023-06-02 16:41           ` Robert Richter
2023-05-23 23:29 ` [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling - CHANGELOG Terry Bowman
2023-05-24  1:39 ` [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling Terry Bowman

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