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[34.78.232.44]) by smtp.gmail.com with ESMTPSA id u4-20020a05600c00c400b003f4290720d0sm21166093wmm.47.2023.05.15.08.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 08:38:00 -0700 (PDT) Date: Mon, 15 May 2023 15:37:55 +0000 From: Mostafa Saleh To: Eric Auger Cc: qemu-devel@nongnu.org, jean-philippe@linaro.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org Subject: Re: [RFC PATCH v3 05/10] hw/arm/smmuv3: Parse STE config for stage-2 Message-ID: References: <20230401104953.1325983-1-smostafa@google.com> <20230401104953.1325983-6-smostafa@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=smostafa@google.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: iDXq/QeEPi1v Hi Eric, Thanks a lot for taking the time to review the patches. On Mon, May 15, 2023 at 03:03:28PM +0200, Eric Auger wrote: > > > > +/* If stage-1 fault enabled and ptw event targets it. */ > > +#define PTW_FAULT_S1(cfg, event) ((cfg)->record_faults && \ > > + !(event).u.f_walk_eabt.s2) > > +/* If stage-2 fault enabled and ptw event targets it. */ > > +#define PTW_FAULT_S2(cfg, event) ((cfg)->s2cfg.record_faults && \ > > + (event).u.f_walk_eabt.s2) > > + > > +#define PTW_FAULT_ALLOWED(cfg, event) (PTW_FAULT_S1(cfg, event) || \ > > + PTW_FAULT_S2(cfg, event)) > The name of the macro does not really reflect what it tests. I would > suggest PTW_RECORD_FAULT and PTW_RECORD_S1|S2_FAULT > I would also suggest (cfg->stage == 1) ?  PTW_RECORD_S1_FAULT(cfg, > event) :  PTW_RECORD_S2_FAULT(cfg, event) > > PTW_FAULT_S1() and PTW_FAULT_S2() are not used anywhere else. > > I would simplify PTW_RECORD_FAULT(cfg)  (cfg->stage == 1) ? > (cfg)->record_faults:  (cfg)->s2cfg.record_faults Yes, this is much simpler. I am wondering as stage-2 only SMMUs can have stage-1 faults as described in (IHI 0070.E.a) "3.4 Address sizes". If the input address of a transaction exceeds the size of the IAS. I guess this means that the fault record in this case is still controlled by S2R although it is stage-1 fault as there is no CD or stage-1 config. Thanks, Mostafa