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From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Quentin Perret , Will Deacon , Fuad Tabba Subject: Re: [PATCH 02/17] arm64: Add KVM_HVHE capability and has_hvhe() predicate Message-ID: References: <20221020090727.3669908-1-maz@kernel.org> <20221020090727.3669908-3-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221020090727.3669908-3-maz@kernel.org> X-Migadu-Flow: FLOW_OUT On Thu, Oct 20, 2022 at 10:07:12AM +0100, Marc Zyngier wrote: > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index a3959e9f7d55..efac89c4c548 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1932,6 +1932,15 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) > write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); > } > > +static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, > + int __unused) > +{ > + u64 val; > + > + val = arm64_sw_feature_override.val & arm64_sw_feature_override.mask; > + return cpuid_feature_extract_unsigned_field(val, ARM64_SW_FEATURE_OVERRIDE_HVHE); > +} Does this need to test ID_AA64MMFR1_EL1.VH as well? Otherwise I don't see what would stop us from attempting hVHE on a system with asymmetric support for VHE, as the software override was only evaluated on the boot CPU. > + > #ifdef CONFIG_ARM64_PAN > static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) > { > @@ -2642,6 +2651,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .cpu_enable = cpu_trap_el0_impdef, > }, > + { > + .desc = "VHE for hypervisor only", > + .capability = ARM64_KVM_HVHE, > + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, > + .matches = hvhe_possible, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index f1c0347ec31a..cee2be85b89b 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -43,6 +43,7 @@ HAS_TLB_RANGE > HAS_VIRT_HOST_EXTN > HAS_WFXT > HW_DBM > +KVM_HVHE > KVM_PROTECTED_MODE > MISMATCHED_CACHE_TYPE > MTE > -- > 2.34.1 > -- Thanks, Oliver From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 656BDC77B7A for ; Thu, 1 Jun 2023 07:02:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GmMbBciJV+ULbuLsf9Brfwfnu8PA9oz0sE/1yjBR0V8=; b=TcC4ahNnBbVwbo QNaDjJWn2EAtnCFjC51QvgxX8uo1TF4OtEMEPD6PcBi9+1YNfe5H16CleiU+K2gzvP/rSbtJ3rAny /pXo2ZhkhPn8hPJy0a3xHaeC97RQh0NPHuB7lnOyvxYA7cjZvbcTwnX0iOHW6Dr0f0rx3ku2Q3qol /oL9P4lVGFqfxIHbGREhxqSvjLDIvMPvgMMDO2y761PBLjHp4S9bnxn9im5RBrirccpAi97QHVOr4 SWlTslr5cdOVkSH8/4nGcdZiLfoQG0C2JEl9vhydSy2QPPMr+H5Zh/luVcki4fcq9azEV5eACXX4c bW0fJ8A+pIEJF3nSrKpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q4cJw-002IAZ-1B; Thu, 01 Jun 2023 07:02:04 +0000 Received: from out-10.mta1.migadu.com ([95.215.58.10]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q4cJs-002I8p-2R for linux-arm-kernel@lists.infradead.org; Thu, 01 Jun 2023 07:02:02 +0000 Date: Thu, 1 Jun 2023 07:01:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1685602914; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=plr4C16SSJbKZ59AieGvFJiPtYheTw7pGAQ68J2Djz8=; b=C7FXcOcqsYSeBr4NAXtbvcxKb0OL0ZNSvL9RHTKGcT4hdyOL9Y32dz6uHpohEy6iOhUg4N C72iagtr2eRQ54LHUg0d9WCFov4IiviKD1ws6ZtPU27I3oQo0gQY67+fbdo5IwHqZFVQcj RouUPWaFLIDHHGuuKBJm6IF/8r0WJZw= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Quentin Perret , Will Deacon , Fuad Tabba Subject: Re: [PATCH 02/17] arm64: Add KVM_HVHE capability and has_hvhe() predicate Message-ID: References: <20221020090727.3669908-1-maz@kernel.org> <20221020090727.3669908-3-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221020090727.3669908-3-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230601_000201_479998_AA2FF527 X-CRM114-Status: GOOD ( 16.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 20, 2022 at 10:07:12AM +0100, Marc Zyngier wrote: > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index a3959e9f7d55..efac89c4c548 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1932,6 +1932,15 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) > write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); > } > > +static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, > + int __unused) > +{ > + u64 val; > + > + val = arm64_sw_feature_override.val & arm64_sw_feature_override.mask; > + return cpuid_feature_extract_unsigned_field(val, ARM64_SW_FEATURE_OVERRIDE_HVHE); > +} Does this need to test ID_AA64MMFR1_EL1.VH as well? Otherwise I don't see what would stop us from attempting hVHE on a system with asymmetric support for VHE, as the software override was only evaluated on the boot CPU. > + > #ifdef CONFIG_ARM64_PAN > static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) > { > @@ -2642,6 +2651,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .cpu_enable = cpu_trap_el0_impdef, > }, > + { > + .desc = "VHE for hypervisor only", > + .capability = ARM64_KVM_HVHE, > + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, > + .matches = hvhe_possible, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index f1c0347ec31a..cee2be85b89b 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -43,6 +43,7 @@ HAS_TLB_RANGE > HAS_VIRT_HOST_EXTN > HAS_WFXT > HW_DBM > +KVM_HVHE > KVM_PROTECTED_MODE > MISMATCHED_CACHE_TYPE > MTE > -- > 2.34.1 > -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel