From: Sean Christopherson <seanjc@google.com>
To: Like Xu <like.xu.linux@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Subject: Re: [PATCH v6 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met
Date: Thu, 1 Jun 2023 17:50:41 -0700 [thread overview]
Message-ID: <ZHk84Ts9txpz5djC@google.com> (raw)
In-Reply-To: <20230530060423.32361-6-likexu@tencent.com>
On Tue, May 30, 2023, Like Xu wrote:
> According to Intel SDM, "Intel Core Solo and Intel Core Duo processors
> support base level functionality identified by version ID of 1. Processors
> based on Intel Core microarchitecture support, at a minimum, the base
> level functionality of architectural performance monitoring." Those
> antique processors mentioned above all had at least two GP counters,
> subsequent processors had more and more GP counters, and given KVM's
> quirky handling of MSR_P6_PERFCTR0/1, the value of MIN_NR_GP_COUNTERS
> for the Intel Arch PMU can safely be 2.
Not sure what you mean by "safely", but I don't think this is correct. KVM can,
and more importantly has up until this point, supported a vPMU so long as the CPU
has at least one counter. Perf's support for P6/Core CPUs does appear to expect
and require 2 counters, but unless I'm misreading arch/x86/events/intel/core.c,
perf will happily chug along with a single counter when running on a modern CPU.
I doubt such a CPU exists in real silicon, but I can certainly imagine a virtual
CPU being configured with a single counter, and this change would break such a
setup.
And *if* we really want to raise the minimum to '2', that should be done in a
separate commit. But I don't see any reason to force the issue.
No need to send v7 just for this, I can fixup when applying (planning on reviewing
the series tomorrow).
next prev parent reply other threads:[~2023-06-02 0:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 6:04 [PATCH v6 00/10] KVM: x86: Add AMD Guest PerfMonV2 PMU support Like Xu
2023-05-30 6:04 ` [PATCH v6 01/10] KVM: x86/pmu: Expose reprogram_counters() in pmu.h Like Xu
2023-05-30 6:04 ` [PATCH v6 02/10] KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits Like Xu
2023-06-02 21:59 ` Sean Christopherson
2023-05-30 6:04 ` [PATCH v6 03/10] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic Like Xu
2023-06-02 23:23 ` Sean Christopherson
2023-05-30 6:04 ` [PATCH v6 04/10] KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled Like Xu
2023-05-30 6:04 ` [PATCH v6 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met Like Xu
2023-06-02 0:50 ` Sean Christopherson [this message]
2023-05-30 6:04 ` [PATCH v6 06/10] KVM: x86/pmu: Forget PERFCTR_CORE if the min " Like Xu
2023-05-30 6:04 ` [PATCH v6 07/10] KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap Like Xu
2023-05-30 6:04 ` [PATCH v6 08/10] KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag Like Xu
2023-05-30 6:04 ` [PATCH v6 09/10] KVM: x86/svm/pmu: Add AMD PerfMonV2 support Like Xu
2023-05-30 6:04 ` [PATCH v6 10/10] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 Like Xu
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