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List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 27, 2023 at 11:14:30AM -0700, Evan Green wrote: > On Tue, Jun 27, 2023 at 7:38 AM Samuel Ortiz wrote: > > > > From: "Hongren (Zenithal) Zheng" > > > > This patch parses Zb/Zk related string from DT and > > output them in cpuinfo > > > > One thing worth noting is that if DT provides zk, > > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > > > Note that zk is a valid extension name and the current > > DT binding spec allows this. > > > > This patch also changes the logical id of > > existing multi-letter extensions and adds a statement > > that instead of logical id compatibility, the order > > is needed. > > > > There currently lacks a mechanism to merge them when > > producing cpuinfo. Namely if you provide a riscv,isa > > "rv64imafdc_zk_zks", the cpuinfo output would be > > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > > _zksh_zkt" > > > > Tested-by: Jiatai He > > Signed-off-by: Hongren (Zenithal) Zheng I think an extra line of your own signed-off-by is needed > > --- > > arch/riscv/include/asm/hwcap.h | 11 +++++++++++ > > arch/riscv/kernel/cpu.c | 11 +++++++++++ > > arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ > > 3 files changed, 52 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index f041bfa7f6a0..b80ca6e77088 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -53,6 +53,17 @@ > > #define RISCV_ISA_EXT_ZICSR 40 > > #define RISCV_ISA_EXT_ZIFENCEI 41 > > #define RISCV_ISA_EXT_ZIHPM 42 > > +#define RISCV_ISA_EXT_ZBC 43 > > +#define RISCV_ISA_EXT_ZBKB 44 > > +#define RISCV_ISA_EXT_ZBKC 45 > > +#define RISCV_ISA_EXT_ZBKX 46 > > +#define RISCV_ISA_EXT_ZKND 47 > > +#define RISCV_ISA_EXT_ZKNE 48 > > +#define RISCV_ISA_EXT_ZKNH 49 > > +#define RISCV_ISA_EXT_ZKR 50 > > +#define RISCV_ISA_EXT_ZKSED 51 > > +#define RISCV_ISA_EXT_ZKSH 52 > > +#define RISCV_ISA_EXT_ZKT 53 > > > > #define RISCV_ISA_EXT_MAX 64 > > #define RISCV_ISA_EXT_NAME_LEN_MAX 32 > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index a2fc952318e9..10524322a4c0 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -215,7 +215,18 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { > > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > > + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > > + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), > > + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), > > + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), > > __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > > + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), > > + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), > > + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), > > + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), > > + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), > > + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), > > + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), > > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index bdcf460ea53d..447f853a5a4c 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -309,10 +309,40 @@ void __init riscv_fill_hwcap(void) > > SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); > > SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); > > SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); > > + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC); > > SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); > > + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB); > > + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC); > > + SET_ISA_EXT_MAP("zbks", RISCV_ISA_EXT_ZBKX); > > Should "zbks" be "zbkx"? Yes that is a nice catch! > > > SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); > > SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); > > SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > > + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED); > > + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH); > > + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR); > > + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT); > > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKB); > > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKC); > > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKX); > > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKND); > > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNE); > > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNH); > > + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND); > > + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE); > > + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH); > > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKB); > > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKC); > > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKX); > > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSED); > > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSH); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKB); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKC); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKX); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKND); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNE); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNH); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKR); > > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKT); > > It would be nice to consolidate the ones together that search for a > single string and set multiple bits, though I don't have any super > elegant ideas for how off the top of my head.