From: Leo Liang <ycliang@andestech.com>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: <u-boot@lists.denx.de>
Subject: Re: [PATCH 1/2] riscv: andes_plicsw: Fix IPI during OpenSBI invocation
Date: Wed, 5 Jul 2023 02:09:32 +0000 [thread overview]
Message-ID: <ZKTQ3CD/N6QYoFff@ubuntu01> (raw)
In-Reply-To: <20230704111321.12536-1-peterlin@andestech.com>
On Tue, Jul 04, 2023 at 07:13:20PM +0800, Yu Chien Peter Lin wrote:
> On some AE350 boards, we need to explicitly initialize the priority
> registers to a non-zero value so the boot hart can instruct secondary
> harts to jump to OpenSBI.
>
> This patch also updates the information about PLICSW.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> arch/riscv/lib/andes_plicsw.c | 25 ++++++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2023-07-05 2:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 11:13 [PATCH 1/2] riscv: andes_plicsw: Fix IPI during OpenSBI invocation Yu Chien Peter Lin
2023-07-04 11:13 ` [PATCH 2/2] board: ae350: Add missing env variables for booti Yu Chien Peter Lin
2023-07-05 2:10 ` Leo Liang
2023-07-05 2:09 ` Leo Liang [this message]
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