From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D06EBE7C for ; Fri, 4 Aug 2023 17:26:37 +0000 (UTC) Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBD6D469A for ; Fri, 4 Aug 2023 10:26:35 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-686bea20652so2222941b3a.1 for ; Fri, 04 Aug 2023 10:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1691169995; x=1691774795; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=JphLCmILQLQtm6C+8rHqJoDL6onaPDHw9v6WesurCsg=; b=r6q7qAGWzvZUiLJlqMhJLhohj7njHjtcTcRVZt2D2xU9JP3MQJ0/83tKG8aLTI0ohy DbA7Xk80sbDy4V0owZEd4OmS516M139UsF6WaWF8yPHFJWZjYKEO5tU/L/Ls+v5cP+8r zvOoYIwyRhoTMRj8kiRgd72Jh9aGordDV6F0FGpAnOpn+fbtROvFB9Z2LeFqr0WLExyS FKiQCat2x6Kb+JIwFHOM2FneSrIoS4YUyV+Zm5ggxPkme3KBaktv1s1hYG+pbaWG1cTp IuilMWnUL0u3gqEKHw452Mhh2G4Gktwl+EbrJs2NBI1w+ftaSkEbCSjYWJJHNt/IwFjl J+wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691169995; x=1691774795; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=JphLCmILQLQtm6C+8rHqJoDL6onaPDHw9v6WesurCsg=; b=VuseNWYESiJWBR2X763OR82/C70XFOhYMEJC7ciJcdZ7RFNbdp5/n7KlBrkHPO51D6 sbZyugCSjuYr4Mklo0jPOmIvM1G6jb3eXfIC4XJffvXH6hMOlyAF689+l25ydAKl6yHR MUWvcdskyDGN/54q6RLoQ3C1U4PPEji2Jvm0igdtpl3Q94+I1rByRBSujg1rO8jBCcuT 7wRPQG7OLi+RNT6sHlmXDlQXx3n/B76BU3h/43uFh9wjnfrmVwEjdbStPIm4fO9z8K9z jtbzSDAv/OoF/nKig6KH4iIgmEtrBAPipgm1pCnaEZdfZWkhRPnK+/hRw/cVta9Ud7PU O2OA== X-Gm-Message-State: AOJu0YyQ1GbSo7E6QtQtD1aNIt4fs21WppwrrhwbV2TIc16ogxIzh1nU fRX1fzA74bj6Y7bFsCp4ldBYQw== X-Google-Smtp-Source: AGHT+IFY3DK0mTMlQh9d2j8+8rCxpiY2bx9LhdMBgQrVPQ7hwkeFF3l5xqJrFOHDkYksAUT9xQx9aw== X-Received: by 2002:a05:6a00:180c:b0:680:98c:c593 with SMTP id y12-20020a056a00180c00b00680098cc593mr3293062pfa.7.1691169995381; Fri, 04 Aug 2023 10:26:35 -0700 (PDT) Received: from ghost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id v19-20020a62a513000000b006870721fcc5sm1878051pfm.175.2023.08.04.10.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 10:26:34 -0700 (PDT) Date: Fri, 4 Aug 2023 10:26:32 -0700 From: Charlie Jenkins To: Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, bpf@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Anup Patel , Atish Patra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Luke Nelson , Xi Wang , Nam Cao Subject: Re: [PATCH 01/10] RISC-V: Expand instruction definitions Message-ID: References: <20230803-master-refactor-instructions-v4-v1-0-2128e61fa4ff@rivosinc.com> <20230803-master-refactor-instructions-v4-v1-1-2128e61fa4ff@rivosinc.com> <20230804-barterer-heritage-ed191081bc47@wendy> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230804-barterer-heritage-ed191081bc47@wendy> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On Fri, Aug 04, 2023 at 08:59:24AM +0100, Conor Dooley wrote: > On Thu, Aug 03, 2023 at 07:10:26PM -0700, Charlie Jenkins wrote: > > There are many systems across the kernel that rely on directly creating > > and modifying instructions. In order to unify them, create shared > > definitions for instructions and registers. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/insn.h | 2742 +++++++++++++++++++++++++++--- > > "I did a lot of copy-pasting from the RISC-V spec" > > How is anyone supposed to cross check this when there's 1000s of lines > of a diff here? We've had some subtle bugs in some of the definitions in > the past, so I would like to be able to check at this opportune moment > that things are correct. > > > arch/riscv/include/asm/reg.h | 88 + > > arch/riscv/kernel/kgdb.c | 4 +- > > arch/riscv/kernel/probes/simulate-insn.c | 39 +- > > arch/riscv/kernel/vector.c | 2 +- > > You need to at least split this up. I doubt a 2742 change diff for > insn.h was required to make the changes in these 4 files. Yeah it is kind of a nightmare to look at, I will split it up. > > Then after that, it would be so much easier to reason about these > changes if the additions to insn.h happened at the same time as the > removals from the affected locations. > > I would probably split this so that things are done in more stages, > with the larger patches split between changes that require no new > definitions and changes that require moving things to insn.h > > > 5 files changed, 2629 insertions(+), 246 deletions(-) > > What you would want to see if this arrived in your inbox as a reviewer? > > Don't get me wrong, I do like what you are doing here, the BPF JIT > especially is filled with "uhh okay, I guess those offsets are right", > so I don't mean to be discouraging. > > Thanks, > Conor. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Charlie Jenkins Date: Fri, 4 Aug 2023 10:26:32 -0700 Subject: [PATCH 01/10] RISC-V: Expand instruction definitions In-Reply-To: <20230804-barterer-heritage-ed191081bc47@wendy> References: <20230803-master-refactor-instructions-v4-v1-0-2128e61fa4ff@rivosinc.com> <20230803-master-refactor-instructions-v4-v1-1-2128e61fa4ff@rivosinc.com> <20230804-barterer-heritage-ed191081bc47@wendy> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Fri, Aug 04, 2023 at 08:59:24AM +0100, Conor Dooley wrote: > On Thu, Aug 03, 2023 at 07:10:26PM -0700, Charlie Jenkins wrote: > > There are many systems across the kernel that rely on directly creating > > and modifying instructions. In order to unify them, create shared > > definitions for instructions and registers. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/insn.h | 2742 +++++++++++++++++++++++++++--- > > "I did a lot of copy-pasting from the RISC-V spec" > > How is anyone supposed to cross check this when there's 1000s of lines > of a diff here? We've had some subtle bugs in some of the definitions in > the past, so I would like to be able to check at this opportune moment > that things are correct. > > > arch/riscv/include/asm/reg.h | 88 + > > arch/riscv/kernel/kgdb.c | 4 +- > > arch/riscv/kernel/probes/simulate-insn.c | 39 +- > > arch/riscv/kernel/vector.c | 2 +- > > You need to at least split this up. I doubt a 2742 change diff for > insn.h was required to make the changes in these 4 files. Yeah it is kind of a nightmare to look at, I will split it up. > > Then after that, it would be so much easier to reason about these > changes if the additions to insn.h happened at the same time as the > removals from the affected locations. > > I would probably split this so that things are done in more stages, > with the larger patches split between changes that require no new > definitions and changes that require moving things to insn.h > > > 5 files changed, 2629 insertions(+), 246 deletions(-) > > What you would want to see if this arrived in your inbox as a reviewer? > > Don't get me wrong, I do like what you are doing here, the BPF JIT > especially is filled with "uhh okay, I guess those offsets are right", > so I don't mean to be discouraging. > > Thanks, > Conor. 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Fri, 04 Aug 2023 10:26:34 -0700 (PDT) Date: Fri, 4 Aug 2023 10:26:32 -0700 From: Charlie Jenkins To: Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, bpf@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Anup Patel , Atish Patra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Luke Nelson , Xi Wang , Nam Cao Subject: Re: [PATCH 01/10] RISC-V: Expand instruction definitions Message-ID: References: <20230803-master-refactor-instructions-v4-v1-0-2128e61fa4ff@rivosinc.com> <20230803-master-refactor-instructions-v4-v1-1-2128e61fa4ff@rivosinc.com> <20230804-barterer-heritage-ed191081bc47@wendy> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230804-barterer-heritage-ed191081bc47@wendy> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230804_102638_172240_0BB38C00 X-CRM114-Status: GOOD ( 25.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Aug 04, 2023 at 08:59:24AM +0100, Conor Dooley wrote: > On Thu, Aug 03, 2023 at 07:10:26PM -0700, Charlie Jenkins wrote: > > There are many systems across the kernel that rely on directly creating > > and modifying instructions. In order to unify them, create shared > > definitions for instructions and registers. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/insn.h | 2742 +++++++++++++++++++++++++++--- > > "I did a lot of copy-pasting from the RISC-V spec" > > How is anyone supposed to cross check this when there's 1000s of lines > of a diff here? We've had some subtle bugs in some of the definitions in > the past, so I would like to be able to check at this opportune moment > that things are correct. > > > arch/riscv/include/asm/reg.h | 88 + > > arch/riscv/kernel/kgdb.c | 4 +- > > arch/riscv/kernel/probes/simulate-insn.c | 39 +- > > arch/riscv/kernel/vector.c | 2 +- > > You need to at least split this up. I doubt a 2742 change diff for > insn.h was required to make the changes in these 4 files. Yeah it is kind of a nightmare to look at, I will split it up. > > Then after that, it would be so much easier to reason about these > changes if the additions to insn.h happened at the same time as the > removals from the affected locations. > > I would probably split this so that things are done in more stages, > with the larger patches split between changes that require no new > definitions and changes that require moving things to insn.h > > > 5 files changed, 2629 insertions(+), 246 deletions(-) > > What you would want to see if this arrived in your inbox as a reviewer? > > Don't get me wrong, I do like what you are doing here, the BPF JIT > especially is filled with "uhh okay, I guess those offsets are right", > so I don't mean to be discouraging. > > Thanks, > Conor. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv