From: Sean Christopherson <seanjc@google.com>
To: Weijiang Yang <weijiang.yang@intel.com>
Cc: Chao Gao <chao.gao@intel.com>,
pbonzini@redhat.com, peterz@infradead.org, john.allen@amd.com,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
rick.p.edgecombe@intel.com, binbin.wu@linux.intel.com
Subject: Re: [PATCH v4 13/20] KVM:VMX: Emulate read and write to CET MSRs
Date: Thu, 27 Jul 2023 08:20:38 -0700 [thread overview]
Message-ID: <ZMKLRnjCTwqTr/MF@google.com> (raw)
In-Reply-To: <2801b9d6-4f32-c4b2-ae93-c56ffc2b4621@intel.com>
On Thu, Jul 27, 2023, Weijiang Yang wrote:
>
> On 7/27/2023 1:16 PM, Chao Gao wrote:
> > > > > @@ -2402,6 +2417,31 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> > > > > else
> > > > > vmx->pt_desc.guest.addr_a[index / 2] = data;
> > > > > break;
> > > > > +#define VMX_CET_CONTROL_MASK (~GENMASK_ULL(9, 6))
> > > > bits9-6 are reserved for both intel and amd. Shouldn't this check be
> > > > done in the common code?
> > > My thinking is, on AMD platform, bit 63:2 is anyway reserved since it doesn't
> > > support IBT,
> > You can only say
> >
> > bits 5:2 and bits 63:10 are reserved since AMD doens't support IBT.
> >
> > bits 9:6 are reserved regardless of the support of IBT.
> >
> > > so the checks in common code for AMD is enough, when the execution flow comes
> > > here,
> > >
> > > it should be vmx, and need this additional check.
> > The checks against reserved bits are common for AMD and Intel:
> >
> > 1. if SHSTK is supported, bit1:0 are not reserved.
> > 2. if IBT is supported, bit5:2 and bit63:10 are not reserved
> > 3. bit9:6 are always reserved.
> >
> > There is nothing specific to Intel.
+1
> So you want the code to be:
>
> +#define CET_IBT_MASK_BITS (GENMASK_ULL(5, 2) | GENMASK_ULL(63,
> 10))
>
> +#define CET_CTRL_RESERVED_BITS GENMASK(9, 6)
>
> +#define CET_SHSTK_MASK_BITSGENMASK(1, 0)
>
> +if ((!guest_can_use(vcpu, X86_FEATURE_SHSTK) &&
>
> +(data & CET_SHSTK_MASK_BITS)) ||
>
> +(!guest_can_use(vcpu, X86_FEATURE_IBT) &&
>
> +(data & CET_IBT_MASK_BITS)) ||
>
> (data & CET_CTRL_RESERVED_BITS) )
>
> ^^^^^^^^^^^^^^^^^^^^^^^^^
Yes, though I vote to separate each check, e.g.
if (data & CET_CTRL_RESERVED_BITS)
return 1;
if (!guest_can_use(vcpu, X86_FEATURE_SHSTK) && (data & CET_SHSTK_MASK_BITS))
return 1;
if (!guest_can_use(vcpu, X86_FEATURE_IBT) && (data & CET_IBT_MASK_BITS))
return 1;
I would expect the code generation to be similar, if not outright identical, and
IMO it's easier to quickly understand the flow if each check is a separate if-statement.
next prev parent reply other threads:[~2023-07-27 15:20 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 3:03 [PATCH v4 00/20] Enable CET Virtualization Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 01/20] x86/cpufeatures: Add CPU feature flags for shadow stacks Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 02/20] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 03/20] KVM:x86: Report XSS as to-be-saved if there are supported features Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 04/20] KVM:x86: Refresh CPUID on write to guest MSR_IA32_XSS Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 05/20] KVM:x86: Initialize kvm_caps.supported_xss Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 06/20] KVM:x86: Load guest FPU state when access XSAVE-managed MSRs Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 07/20] KVM:x86: Add fault checks for guest CR4.CET setting Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 08/20] KVM:x86: Report KVM supported CET MSRs as to-be-saved Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 09/20] KVM:x86: Add common code of CET MSR access Yang Weijiang
2023-07-26 7:33 ` Chao Gao
2023-07-26 8:26 ` Yang, Weijiang
2023-07-26 13:46 ` Chao Gao
2023-07-27 6:06 ` Yang, Weijiang
2023-07-27 7:41 ` Chao Gao
2023-07-27 16:58 ` Sean Christopherson
2023-07-21 3:03 ` [PATCH v4 10/20] KVM:x86: Make guest supervisor states as non-XSAVE managed Yang Weijiang
2023-07-24 8:26 ` Chao Gao
2023-07-24 13:50 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 11/20] KVM:x86: Save and reload GUEST_SSP to/from SMRAM Yang Weijiang
2023-07-24 9:13 ` Chao Gao
2023-07-24 14:16 ` Yang, Weijiang
2023-07-24 14:26 ` Sean Christopherson
2023-07-21 3:03 ` [PATCH v4 12/20] KVM:VMX: Introduce CET VMCS fields and control bits Yang Weijiang
2023-07-27 5:26 ` Chao Gao
2023-07-27 7:13 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 13/20] KVM:VMX: Emulate read and write to CET MSRs Yang Weijiang
2023-07-26 8:06 ` Chao Gao
2023-07-27 3:19 ` Yang, Weijiang
2023-07-27 5:16 ` Chao Gao
2023-07-27 7:10 ` Yang, Weijiang
2023-07-27 15:20 ` Sean Christopherson [this message]
2023-07-28 0:43 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 14/20] KVM:VMX: Set up interception for " Yang Weijiang
2023-07-26 8:30 ` Chao Gao
2023-07-27 3:48 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 15/20] KVM:VMX: Save host MSR_IA32_S_CET to VMCS field Yang Weijiang
2023-07-26 8:47 ` Chao Gao
2023-07-26 14:05 ` Sean Christopherson
2023-07-27 7:29 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 16/20] KVM:x86: Optimize CET supervisor SSP save/reload Yang Weijiang
2023-07-27 3:27 ` Chao Gao
2023-07-27 6:23 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 17/20] KVM:x86: Enable CET virtualization for VMX and advertise to userspace Yang Weijiang
2023-07-27 6:32 ` Chao Gao
2023-07-27 7:26 ` Yang, Weijiang
2023-07-21 3:03 ` [PATCH v4 18/20] KVM:x86: Enable guest CET supervisor xstate bit support Yang Weijiang
2023-07-27 8:03 ` Chao Gao
2023-07-21 3:03 ` [PATCH v4 19/20] KVM:nVMX: Refine error code injection to nested VM Yang Weijiang
2023-07-21 3:03 ` [PATCH v4 20/20] KVM:nVMX: Enable CET support for " Yang Weijiang
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