From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7BD05C001B0 for ; Mon, 7 Aug 2023 12:30:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9927B10E288; Mon, 7 Aug 2023 12:30:51 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E35E10E288; Mon, 7 Aug 2023 12:30:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691411415; x=1722947415; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=IA6vm99nYN9bBFgGHAGn5CJWx5F3Pxs12A9Zq94PDn8=; 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charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Intel-gfx] [PATCH 10/20] drm/i915/dp: Add functions to get min/max src input bpc with DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Aug 04, 2023 at 09:42:34AM +0530, Nautiyal, Ankit K wrote: > > On 8/2/2023 5:35 PM, Lisovskiy, Stanislav wrote: > > On Fri, Jul 28, 2023 at 09:41:40AM +0530, Ankit Nautiyal wrote: > > > Separate out functions for getting maximum and minimum input BPC based > > > on platforms, when DSC is used. > > > > > > Signed-off-by: Ankit Nautiyal > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++------ > > > 1 file changed, 30 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 7ec8a478e000..f41de126a8d3 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -1535,6 +1535,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, > > > return -EINVAL; > > > } > > > +static > > > +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) > > > +{ > > > + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ > > > + if (DISPLAY_VER(i915) >= 12) > > > + return 12; > > > + if (DISPLAY_VER(i915) == 11) > > > + return 10; > > > + > > > + return 0; > > > +} > > > + > > > int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) > > > { > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > @@ -1542,11 +1554,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) > > > u8 dsc_bpc[3] = {0}; > > > u8 dsc_max_bpc; > > > - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ > > > - if (DISPLAY_VER(i915) >= 12) > > > - dsc_max_bpc = min_t(u8, 12, max_req_bpc); > > > - else > > > - dsc_max_bpc = min_t(u8, 10, max_req_bpc); > > > + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); > > > + > > > + if (!dsc_max_bpc) > > > + return dsc_max_bpc; > > > + > > > + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); > > > num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, > > > dsc_bpc); > > > @@ -1674,6 +1687,16 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, > > > return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); > > > } > > > +static > > > +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) > > > +{ > > > + /* Min DSC Input BPC for ICL+ is 8 */ > > > + if (DISPLAY_VER(i915) >= 11) > > > + return 8; > > > + > > > + return 0; > > So does it mean that for anything below gen 11, there is no limit at all? > > Also it means that the condition below will never be executed for gen <= 11. > > Hmm. Bspec says min bpc is 8 for DSC, so idea is to have min bpc as 8 when > DSC is used. > > This is supposed to be called only if DSC is supported, so perhaps HAS_DSC > can be used? > > return HAS_DSC(dev_priv) ? 8 : 0; > > > Regards, > > Ankit Yeah, I think that might be better, since we actually car about if we support DSC or not. HAS_DSC should do all the magic, to determine if we support it or not.. Stan > > > > > Stan > > > > > +} > > > + > > > int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > > > struct intel_crtc_state *pipe_config, > > > struct drm_connector_state *conn_state, > > > @@ -1707,10 +1730,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > > > pipe_bpp = pipe_config->pipe_bpp; > > > } > > > - /* Min Input BPC for ICL+ is 8 */ > > > - if (pipe_bpp < 8 * 3) { > > > + if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) { > > > drm_dbg_kms(&dev_priv->drm, > > > - "No DSC support for less than 8bpc\n"); > > > + "Computed BPC less than min supported by source for DSC\n"); > > > return -EINVAL; > > > } > > > -- > > > 2.40.1 > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11B9CC001DF for ; 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a="374207759" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="374207759" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2023 05:30:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10794"; a="734087145" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="734087145" Received: from unknown (HELO intel.com) ([10.237.72.65]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2023 05:30:12 -0700 Date: Mon, 7 Aug 2023 15:30:09 +0300 From: "Lisovskiy, Stanislav" To: "Nautiyal, Ankit K" Subject: Re: [PATCH 10/20] drm/i915/dp: Add functions to get min/max src input bpc with DSC Message-ID: References: <20230728041150.2524032-1-ankit.k.nautiyal@intel.com> <20230728041150.2524032-11-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, anusha.srivatsa@intel.com, dri-devel@lists.freedesktop.org, navaremanasi@google.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Aug 04, 2023 at 09:42:34AM +0530, Nautiyal, Ankit K wrote: > > On 8/2/2023 5:35 PM, Lisovskiy, Stanislav wrote: > > On Fri, Jul 28, 2023 at 09:41:40AM +0530, Ankit Nautiyal wrote: > > > Separate out functions for getting maximum and minimum input BPC based > > > on platforms, when DSC is used. > > > > > > Signed-off-by: Ankit Nautiyal > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++------ > > > 1 file changed, 30 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 7ec8a478e000..f41de126a8d3 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -1535,6 +1535,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, > > > return -EINVAL; > > > } > > > +static > > > +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) > > > +{ > > > + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ > > > + if (DISPLAY_VER(i915) >= 12) > > > + return 12; > > > + if (DISPLAY_VER(i915) == 11) > > > + return 10; > > > + > > > + return 0; > > > +} > > > + > > > int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) > > > { > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > @@ -1542,11 +1554,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) > > > u8 dsc_bpc[3] = {0}; > > > u8 dsc_max_bpc; > > > - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ > > > - if (DISPLAY_VER(i915) >= 12) > > > - dsc_max_bpc = min_t(u8, 12, max_req_bpc); > > > - else > > > - dsc_max_bpc = min_t(u8, 10, max_req_bpc); > > > + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); > > > + > > > + if (!dsc_max_bpc) > > > + return dsc_max_bpc; > > > + > > > + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); > > > num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, > > > dsc_bpc); > > > @@ -1674,6 +1687,16 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, > > > return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); > > > } > > > +static > > > +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) > > > +{ > > > + /* Min DSC Input BPC for ICL+ is 8 */ > > > + if (DISPLAY_VER(i915) >= 11) > > > + return 8; > > > + > > > + return 0; > > So does it mean that for anything below gen 11, there is no limit at all? > > Also it means that the condition below will never be executed for gen <= 11. > > Hmm. Bspec says min bpc is 8 for DSC, so idea is to have min bpc as 8 when > DSC is used. > > This is supposed to be called only if DSC is supported, so perhaps HAS_DSC > can be used? > > return HAS_DSC(dev_priv) ? 8 : 0; > > > Regards, > > Ankit Yeah, I think that might be better, since we actually car about if we support DSC or not. HAS_DSC should do all the magic, to determine if we support it or not.. Stan > > > > > Stan > > > > > +} > > > + > > > int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > > > struct intel_crtc_state *pipe_config, > > > struct drm_connector_state *conn_state, > > > @@ -1707,10 +1730,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > > > pipe_bpp = pipe_config->pipe_bpp; > > > } > > > - /* Min Input BPC for ICL+ is 8 */ > > > - if (pipe_bpp < 8 * 3) { > > > + if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) { > > > drm_dbg_kms(&dev_priv->drm, > > > - "No DSC support for less than 8bpc\n"); > > > + "Computed BPC less than min supported by source for DSC\n"); > > > return -EINVAL; > > > } > > > -- > > > 2.40.1 > > >