From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F006CC001DF for ; Mon, 7 Aug 2023 12:35:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E9B7510E289; Mon, 7 Aug 2023 12:35:49 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4523489F27; Mon, 7 Aug 2023 12:35:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691411729; x=1722947729; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=diHS1Ly5/jv//8ADbxP9bBZM+0FQ4EJqdRg8DkLJw8Y=; b=dvQw8RQA8KLni27uVgXdJBLCImi3I5antKnzLcmqY3EH7336F1d4gqaN xOaVWxXb6ZfLj99/wqfaL2uWIJWJdanNH3k9jiRUVZeiJ3V3UCUU9Z/Yl x3YR5c2+QtI5qBBZFqcMMRYTOeIqXIoDoo54EHuF25SmX4ptFnA73jIyy yDQy8QEQJpvW8/62sN7F8YBF+NUu/LPV7EpqHTLcsjfNRW72ouVohBnCL o+g5tHNJ9cgJaHB4DMCRRa89Wz1xUt6Xl854vzFFCOdin+GzWAl2sSnAL iWBP3znxe/lG4GyFHFRjy15flQ9PbdkmbyFIxSwcZcLQVFDrrU6h4inKG Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10794"; a="367990622" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="367990622" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2023 05:35:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10794"; a="854651907" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="854651907" Received: from unknown (HELO intel.com) ([10.237.72.65]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2023 05:35:17 -0700 Date: Mon, 7 Aug 2023 15:35:14 +0300 From: "Lisovskiy, Stanislav" To: Ankit Nautiyal Message-ID: References: <20230728041150.2524032-1-ankit.k.nautiyal@intel.com> <20230728041150.2524032-17-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230728041150.2524032-17-ankit.k.nautiyal@intel.com> Subject: Re: [Intel-gfx] [PATCH 16/20] drm/i915/dp: Separate out function to get compressed bpp with joiner X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Jul 28, 2023 at 09:41:46AM +0530, Ankit Nautiyal wrote: > Pull the code to get joiner constraints on maximum compressed bpp into > separate function. > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dp.c | 54 ++++++++++++++----------- > 1 file changed, 30 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index b296db026fd8..9720d32c6301 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -740,6 +740,32 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p > return bits_per_pixel; > } Reviewed-by: Stanislav Lisovskiy > > +static > +u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, > + u32 mode_clock, u32 mode_hdisplay, > + bool bigjoiner) > +{ > + u32 max_bpp_small_joiner_ram; > + > + /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ > + max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; > + > + if (bigjoiner) { > + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; > + /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ > + int ppc = 2; > + u32 max_bpp_bigjoiner = > + i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / > + intel_dp_mode_to_fec_clock(mode_clock); > + > + max_bpp_small_joiner_ram *= 2; > + > + return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); > + } > + > + return max_bpp_small_joiner_ram; > +} > + > u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, > u32 link_clock, u32 lane_count, > u32 mode_clock, u32 mode_hdisplay, > @@ -748,7 +774,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, > u32 pipe_bpp, > u32 timeslots) > { > - u32 bits_per_pixel, max_bpp_small_joiner_ram; > + u32 bits_per_pixel, joiner_max_bpp; > > /* > * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* > @@ -788,29 +814,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, > (link_clock * lane_count * 8), > intel_dp_mode_to_fec_clock(mode_clock)); > > - /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ > - max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / > - mode_hdisplay; > - > - if (bigjoiner) > - max_bpp_small_joiner_ram *= 2; > - > - /* > - * Greatest allowed DSC BPP = MIN (output BPP from available Link BW > - * check, output bpp from small joiner RAM check) > - */ > - bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); > - > - if (bigjoiner) { > - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; > - /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ > - int ppc = 2; > - u32 max_bpp_bigjoiner = > - i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / > - intel_dp_mode_to_fec_clock(mode_clock); > - > - bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner); > - } > + joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock, > + mode_hdisplay, bigjoiner); > + bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); > > bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); > > -- > 2.40.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23FC5C001B0 for ; Mon, 7 Aug 2023 12:35:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F360010E290; Mon, 7 Aug 2023 12:35:49 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4523489F27; Mon, 7 Aug 2023 12:35:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691411729; x=1722947729; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=diHS1Ly5/jv//8ADbxP9bBZM+0FQ4EJqdRg8DkLJw8Y=; b=dvQw8RQA8KLni27uVgXdJBLCImi3I5antKnzLcmqY3EH7336F1d4gqaN xOaVWxXb6ZfLj99/wqfaL2uWIJWJdanNH3k9jiRUVZeiJ3V3UCUU9Z/Yl x3YR5c2+QtI5qBBZFqcMMRYTOeIqXIoDoo54EHuF25SmX4ptFnA73jIyy yDQy8QEQJpvW8/62sN7F8YBF+NUu/LPV7EpqHTLcsjfNRW72ouVohBnCL o+g5tHNJ9cgJaHB4DMCRRa89Wz1xUt6Xl854vzFFCOdin+GzWAl2sSnAL iWBP3znxe/lG4GyFHFRjy15flQ9PbdkmbyFIxSwcZcLQVFDrrU6h4inKG Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10794"; a="367990622" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="367990622" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2023 05:35:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10794"; a="854651907" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="854651907" Received: from unknown (HELO intel.com) ([10.237.72.65]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2023 05:35:17 -0700 Date: Mon, 7 Aug 2023 15:35:14 +0300 From: "Lisovskiy, Stanislav" To: Ankit Nautiyal Subject: Re: [PATCH 16/20] drm/i915/dp: Separate out function to get compressed bpp with joiner Message-ID: References: <20230728041150.2524032-1-ankit.k.nautiyal@intel.com> <20230728041150.2524032-17-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230728041150.2524032-17-ankit.k.nautiyal@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, anusha.srivatsa@intel.com, dri-devel@lists.freedesktop.org, navaremanasi@google.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Jul 28, 2023 at 09:41:46AM +0530, Ankit Nautiyal wrote: > Pull the code to get joiner constraints on maximum compressed bpp into > separate function. > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dp.c | 54 ++++++++++++++----------- > 1 file changed, 30 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index b296db026fd8..9720d32c6301 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -740,6 +740,32 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p > return bits_per_pixel; > } Reviewed-by: Stanislav Lisovskiy > > +static > +u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, > + u32 mode_clock, u32 mode_hdisplay, > + bool bigjoiner) > +{ > + u32 max_bpp_small_joiner_ram; > + > + /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ > + max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; > + > + if (bigjoiner) { > + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; > + /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ > + int ppc = 2; > + u32 max_bpp_bigjoiner = > + i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / > + intel_dp_mode_to_fec_clock(mode_clock); > + > + max_bpp_small_joiner_ram *= 2; > + > + return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); > + } > + > + return max_bpp_small_joiner_ram; > +} > + > u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, > u32 link_clock, u32 lane_count, > u32 mode_clock, u32 mode_hdisplay, > @@ -748,7 +774,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, > u32 pipe_bpp, > u32 timeslots) > { > - u32 bits_per_pixel, max_bpp_small_joiner_ram; > + u32 bits_per_pixel, joiner_max_bpp; > > /* > * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* > @@ -788,29 +814,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, > (link_clock * lane_count * 8), > intel_dp_mode_to_fec_clock(mode_clock)); > > - /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ > - max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / > - mode_hdisplay; > - > - if (bigjoiner) > - max_bpp_small_joiner_ram *= 2; > - > - /* > - * Greatest allowed DSC BPP = MIN (output BPP from available Link BW > - * check, output bpp from small joiner RAM check) > - */ > - bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); > - > - if (bigjoiner) { > - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; > - /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ > - int ppc = 2; > - u32 max_bpp_bigjoiner = > - i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / > - intel_dp_mode_to_fec_clock(mode_clock); > - > - bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner); > - } > + joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock, > + mode_hdisplay, bigjoiner); > + bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); > > bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); > > -- > 2.40.1 >