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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/irq: add dedicated intel_display_irq_init()
Date: Tue, 8 Aug 2023 16:58:12 -0400	[thread overview]
Message-ID: <ZNKsZD7z3JXsnwYP@intel.com> (raw)
In-Reply-To: <45c247c9f5104f3e25bd8913644402a11ec3afaf.1691509966.git.jani.nikula@intel.com>

On Tue, Aug 08, 2023 at 06:53:28PM +0300, Jani Nikula wrote:
> Continue splitting display from the rest.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_driver.c |  2 ++
>  .../gpu/drm/i915/display/intel_display_irq.c    | 17 +++++++++++++++++
>  .../gpu/drm/i915/display/intel_display_irq.h    |  2 ++
>  drivers/gpu/drm/i915/i915_irq.c                 | 17 -----------------
>  4 files changed, 21 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index b909814ae02b..8f144d4d3c39 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -28,6 +28,7 @@
>  #include "intel_crtc.h"
>  #include "intel_display_debugfs.h"
>  #include "intel_display_driver.h"
> +#include "intel_display_irq.h"
>  #include "intel_display_power.h"
>  #include "intel_display_types.h"
>  #include "intel_dkl_phy.h"
> @@ -177,6 +178,7 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915)
>  	if (!HAS_DISPLAY(i915))
>  		return;
>  
> +	intel_display_irq_init(i915);

nice clean up, even the order of the calls stayed absolutely the same


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  	intel_dkl_phy_init(i915);
>  	intel_color_init_hooks(i915);
>  	intel_init_cdclk_hooks(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index e6f172cc665a..168f6d4ce208 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1699,3 +1699,20 @@ void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  			   GEN11_DISPLAY_IRQ_ENABLE);
>  }
>  
> +void intel_display_irq_init(struct drm_i915_private *i915)
> +{
> +	i915->drm.vblank_disable_immediate = true;
> +
> +	/*
> +	 * Most platforms treat the display irq block as an always-on power
> +	 * domain. vlv/chv can disable it at runtime and need special care to
> +	 * avoid writing any of the display block registers outside of the power
> +	 * domain. We defer setting up the display irqs in this case to the
> +	 * runtime pm.
> +	 */
> +	i915->display_irqs_enabled = true;
> +	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> +		i915->display_irqs_enabled = false;
> +
> +	intel_hotplug_irq_init(i915);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index 874893f4f16d..8a2d069d3aac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -78,4 +78,6 @@ void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_
>  void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]);
>  void i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 pipe_stats[I915_MAX_PIPES]);
>  
> +void intel_display_irq_init(struct drm_i915_private *i915);
> +
>  #endif /* __INTEL_DISPLAY_IRQ_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 512fc0ef94a4..1723c215dcf6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1343,23 +1343,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
>  	if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)
>  		to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16;
> -
> -	if (!HAS_DISPLAY(dev_priv))
> -		return;
> -
> -	dev_priv->drm.vblank_disable_immediate = true;
> -
> -	/* Most platforms treat the display irq block as an always-on
> -	 * power domain. vlv/chv can disable it at runtime and need
> -	 * special care to avoid writing any of the display block registers
> -	 * outside of the power domain. We defer setting up the display irqs
> -	 * in this case to the runtime pm.
> -	 */
> -	dev_priv->display_irqs_enabled = true;
> -	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -		dev_priv->display_irqs_enabled = false;
> -
> -	intel_hotplug_irq_init(dev_priv);
>  }
>  
>  /**
> -- 
> 2.39.2
> 

  reply	other threads:[~2023-08-08 20:58 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-08 15:53 [Intel-gfx] [PATCH 0/4] drm/i915/irq: cleanups Jani Nikula
2023-08-08 15:53 ` [Intel-gfx] [PATCH 1/4] drm/i915/irq: add dedicated intel_display_irq_init() Jani Nikula
2023-08-08 20:58   ` Rodrigo Vivi [this message]
2023-08-08 15:53 ` [Intel-gfx] [PATCH 2/4] drm/i915/irq: add dg1_de_irq_postinstall() Jani Nikula
2023-08-08 21:00   ` Rodrigo Vivi
2023-08-08 15:53 ` [Intel-gfx] [PATCH 3/4] drm/i915/irq: add ilk_de_irq_postinstall() Jani Nikula
2023-08-08 21:02   ` Rodrigo Vivi
2023-08-08 15:53 ` [Intel-gfx] [PATCH 4/4] drm/i915/irq: move all PCH irq postinstall calls to display code Jani Nikula
2023-08-08 21:06   ` Rodrigo Vivi
2023-08-10 12:24     ` Jani Nikula
2023-08-08 19:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/irq: cleanups Patchwork
2023-08-08 19:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-08 19:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-09  5:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-08-09 11:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/irq: cleanups (rev2) Patchwork
2023-08-09 11:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-09 11:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-10 11:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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