From: Leo Liang <ycliang@andestech.com>
To: Minda Chen <minda.chen@starfivetech.com>
Cc: "Pali Rohár" <pali@kernel.org>, "Rick Chen" <rick@andestech.com>,
"Torsten Duwe" <duwe@suse.de>, "Bin Meng" <bmeng.cn@gmail.com>,
u-boot@lists.denx.de, "Mason Huo" <mason.huo@starfivetech.com>
Subject: Re: [RESEND, v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
Date: Wed, 9 Aug 2023 15:04:16 +0800 [thread overview]
Message-ID: <ZNM6cFFi7Y_jsreZ@swlinux02> (raw)
In-Reply-To: <20230807085338.27119-4-minda.chen@starfivetech.com>
On Mon, Aug 07, 2023 at 04:53:37PM +0800, Minda Chen wrote:
> Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
> SYS_CACHE_SHIFT_6 to enable it.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> arch/riscv/cpu/jh7110/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2023-08-09 7:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-07 8:53 [RESEND,v1 0/4] Add StarFive VF2 USB host support Minda Chen
2023-08-07 8:53 ` [RESEND, v1 1/4] pci: plda: Get correct ECAM offset in multiple PCIe RC case Minda Chen
2023-08-09 7:02 ` [RESEND,v1 " Leo Liang
2023-08-07 8:53 ` [RESEND,v1 2/4] riscv: dts: starfive: Enable pcie0 dts node Minda Chen
2023-08-09 7:03 ` Leo Liang
2023-08-07 8:53 ` [RESEND, v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE Minda Chen
2023-08-07 10:18 ` Bin Meng
2023-08-09 7:04 ` Leo Liang [this message]
2023-08-07 8:53 ` [RESEND, v1 4/4] configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support Minda Chen
2023-08-09 7:04 ` Leo Liang
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