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Date: Thu, 24 Aug 2023 13:40:14 -0700
From: Saeed Mahameed <saeed@kernel.org>
To: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Cc: netdev@vger.kernel.org, Jakub Kicinski <kuba@kernel.org>,
	Richard Cochran <richardcochran@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Paolo Abeni <pabeni@redhat.com>, Vadim Fedorenko <vadfed@meta.com>,
	Kenneth Klette Jonassen <kenneth.jonassen@bridgetech.tv>
Subject: Re: [PATCH net] net/mlx5: Dynamic cyclecounter shift calculation for
 PTP free running clock
Message-ID: <ZOfALr40vfTt7RJp@x130>
References: <20230821230554.236210-1-rrameshbabu@nvidia.com>
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In-Reply-To: <20230821230554.236210-1-rrameshbabu@nvidia.com>

On 21 Aug 16:05, Rahul Rameshbabu wrote:
>Use a dynamic calculation to determine the shift value for the internal
>timer cyclecounter that will lead to the highest precision frequency
>adjustments. Previously used a constant for the shift value assuming all
>devices supported by the driver had a nominal frequency of 1GHz. However,
>there are devices that operate at different frequencies. The previous shift
>value constant would break the PHC functionality for those devices.
>
>Reported-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>Closes: https://lore.kernel.org/netdev/20230815151507.3028503-1-vadfed@meta.com/
>Fixes: 6a4010927562 ("net/mlx5: Update cyclecounter shift value to improve ptp free running mode precision")
>Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
>Tested-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>

Acked-by: Saeed Mahameed <saeedm@nvidia.com>

I have nothing else in my queue so just go ahead and apply directly to net.

Thanks,
Saeed.