From: Leo Liang <ycliang@andestech.com>
To: Shengyu Qu <wiagn233@outlook.com>
Cc: <rick@andestech.com>, <yanhong.wang@starfivetech.com>,
<sjg@chromium.org>, <andre.przywara@arm.com>,
<xypron.glpk@gmx.de>, <michal.simek@amd.com>,
<marek.vasut+renesas@mailbox.org>, <jbx6244@gmail.com>,
<bmeng@tinylab.org>, <ganboing@gmail.com>,
<minda.chen@starfivetech.com>, <seanga2@gmail.com>,
<u-boot@lists.denx.de>
Subject: Re: [PATCH v6 3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
Date: Mon, 4 Sep 2023 14:24:30 +0800 [thread overview]
Message-ID: <ZPV4HidwSuWuNugk@swlinux02> (raw)
In-Reply-To: <TY3P286MB261133B2CDB503E8F45DD39F981DA@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM>
On Fri, Aug 25, 2023 at 12:25:20AM +0800, Shengyu Qu wrote:
> Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
> would be triggered. Currently, we use DDR ram for SPL malloc arena on
> Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
> SPL malloc arena. To avoid triggering ECC error in this scenario, we
> imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default.
>
> Signed-off-by: Bo Gan <ganboing@gmail.com>
> Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
> ---
> arch/riscv/cpu/jh7110/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2023-09-04 6:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230824162521.22240-1-wiagn233@outlook.com>
2023-08-24 16:25 ` [PATCH v6 1/4] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT Shengyu Qu
2023-08-24 16:31 ` Tom Rini
2023-08-24 16:25 ` [PATCH v6 2/4] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT Shengyu Qu
2023-08-24 16:25 ` [PATCH v6 3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT Shengyu Qu
2023-09-04 6:24 ` Leo Liang [this message]
2023-08-24 16:25 ` [PATCH v6 4/4] configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default Shengyu Qu
2023-09-04 6:28 ` Leo Liang
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