From: Leo Liang <ycliang@andestech.com>
To: Torsten Duwe <duwe@lst.de>
Cc: Rick Chen <rick@andestech.com>,
Yanhong Wang <yanhong.wang@starfivetech.com>,
Xingyu Wu <xingyu.wu@starfivetech.com>,
Mason Huo <mason.huo@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Simon Glass <sjg@chromium.org>, <u-boot@lists.denx.de>
Subject: Re: [PATCH 2/2] riscv: jh7110: enable riscv,timer in the device tree
Date: Mon, 4 Sep 2023 13:58:43 +0800 [thread overview]
Message-ID: <ZPVyE5qVTrJyRLLK@swlinux02> (raw)
In-Reply-To: <20230814160533.D5AE068AFE@verein.lst.de>
On Mon, Aug 14, 2023 at 06:05:33PM +0200, Torsten Duwe wrote:
> The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
> Note that in the device tree.
>
> Signed-off-by: Torsten Duwe <duwe@suse.de>
> ---
> arch/riscv/dts/jh7110.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2023-09-04 6:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-14 16:04 [PATCH 0/2] riscv: jh7110: visionfive2: fix u-boot crash due to missing timer Torsten Duwe
2023-08-14 16:05 ` [PATCH 1/2] riscv: allow riscv timer to be instantiated via device tree Torsten Duwe
2023-09-04 5:57 ` Leo Liang
2023-08-14 16:05 ` [PATCH 2/2] riscv: jh7110: enable riscv,timer in the " Torsten Duwe
2023-09-04 5:58 ` Leo Liang [this message]
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