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[104.199.75.203]) by smtp.gmail.com with ESMTPSA id f1-20020a5d50c1000000b003142e438e8csm4095665wrt.26.2023.09.22.03.34.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 03:34:43 -0700 (PDT) Date: Fri, 22 Sep 2023 10:34:38 +0000 From: Mostafa Saleh To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Eric Auger Subject: Re: [PATCH 3/3] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature Message-ID: References: <20230914145705.1648377-1-peter.maydell@linaro.org> <20230914145705.1648377-4-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230914145705.1648377-4-peter.maydell@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=smostafa@google.com; helo=mail-lf1-x12a.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 15mO7l8EDEhw Hi Peter, On Thu, Sep 14, 2023 at 03:57:05PM +0100, Peter Maydell wrote: > The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is > supported, so we should theoretically have implemented it as part of > the recent S2P work. Fortunately, for us the implementation is a > no-op. > > This feature is about interpretation of the stage 2 page table > descriptor XN bits, which control execute permissions. > > For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and > IOMMUAccessFlags) only indicate read and write; we do not distinguish > data reads from instruction reads outside the CPU proper. In the > SMMU architecture's terms, our interconnect between the client device > and the SMMU doesn't have the ability to convey the INST attribute, > and we therefore use the default value of "data" for this attribute. > > We also do not support the bits in the Stream Table Entry that can > override the on-the-bus transaction attribute permissions (we do not > set SMMU_IDR1.ATTR_PERMS_OVR=1). > > These two things together mean that for our implementation, it never > has to deal with transactions with the INST attribute, and so it can > correctly ignore the XN bits entirely. So we already implement > FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent > that we need to. > > Advertise the presence of the feature in SMMU_IDR3.XNX. > > Signed-off-by: Peter Maydell > --- > hw/arm/smmuv3.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 94d388fc950..d9e639f7c41 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -279,6 +279,7 @@ static void smmuv3_init_regs(SMMUv3State *s) > s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); > > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1); May be this can be guarded when S2P is present? according the UM "In SMMUv3.1 and later, support for this feature is mandatory when stage 2 is supported, that is when SMMU_IDR0.S2P == 1." So I am not sure what it would mean for XNX and S1P only. > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); > -- > 2.34.1 Thanks, Mostafa