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[134.41.202.196]) by smtp.gmail.com with ESMTPSA id h5-20020ac87145000000b00407ffb2c24dsm3369353qtp.63.2023.09.12.09.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 09:32:12 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1qg6J9-002FWM-EW; Tue, 12 Sep 2023 13:32:11 -0300 Date: Tue, 12 Sep 2023 13:32:11 -0300 From: Jason Gunthorpe To: Vasant Hegde Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com, wei.huang2@amd.com, jsnitsel@redhat.com Subject: Re: [PATCH v2 11/11] iommu/amd: Introduce logic to enable/disable IOPF Message-ID: References: <20230911121046.1025732-1-vasant.hegde@amd.com> <20230911121046.1025732-12-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230911121046.1025732-12-vasant.hegde@amd.com> On Mon, Sep 11, 2023 at 12:10:46PM +0000, Vasant Hegde wrote: > diff --git a/drivers/iommu/amd/ppr.c b/drivers/iommu/amd/ppr.c > index 2891f67a6ca0..86c0cb836a71 100644 > --- a/drivers/iommu/amd/ppr.c > +++ b/drivers/iommu/amd/ppr.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > #include "amd_iommu.h" > #include "amd_iommu_types.h" > @@ -306,3 +307,58 @@ int amd_iommu_iopf_remove_device(struct amd_iommu *iommu, struct device *dev) > raw_spin_unlock_irqrestore(&iommu->lock, flags); > return ret; > } > + > +static int amd_iommu_iopf_update(struct device *dev, bool enable) > +{ > + unsigned long flags; > + int ret; > + struct pci_dev *pdev = dev_is_pci(dev) ? to_pci_dev(dev) : NULL; > + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev); > + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); > + struct protection_domain *pdom = amd_iommu_get_pdomain(dev); > + > + if (!pdev || !iommu || !dev_data) > + return -EINVAL; > + > + spin_lock_irqsave(&pdom->lock, flags); > + > + if (enable) { > + ret = amd_iommu_iopf_add_device(iommu, dev); > + if (ret) > + goto out; > + > + dev_data->ppr = true; > + } else { > + ret = amd_iommu_iopf_remove_device(iommu, dev); > + dev_data->ppr = false; > + } > + > + amd_iommu_domain_update(pdom); > + > +out: > + spin_unlock_irqrestore(&pdom->lock, flags); > + return ret; > +} Same remarks as for the SVA, this is in the wrong place. iopf_queue_add_device() should be done when a PRI enabled domain is attached to a device, not in feature things. I also want to remove these too once ARM is fixed.. And the iopf is a device wide thing, it makes no sense that some random pdom->lock is protecting dev_dev->ppr.. amd_iommu_get_pdomain() has improper locking, it needs to hold some kind of dev_data lock to access dev_data->domain. (and really this would all be clearer if it was just written dev_data->domain instead of the redundant function) Jason