From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Luca Coelho <luca@coelho.fi>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 05/11] drm/i915: Check lane count when determining FEC support
Date: Wed, 13 Sep 2023 17:41:48 +0300 [thread overview]
Message-ID: <ZQHKLFQiygq_OKgV@intel.com> (raw)
In-Reply-To: <e73031cb908653d57684775d66771998dedf71b0.camel@coelho.fi>
On Thu, May 25, 2023 at 11:09:30AM +0300, Luca Coelho wrote:
> On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > ICL doesn't support FEC with a x1 DP link. Make sure
> > we don't try to enable FEC in such cases.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 23 ++++++++++++-----------
> > 1 file changed, 12 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index b27b4fb71ed7..9ac199444155 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1218,7 +1218,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> > if (DISPLAY_VER(dev_priv) >= 12)
> > return true;
> >
> > - if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> > + if (DISPLAY_VER(dev_priv) == 11 &&
> > + encoder->port != PORT_A && pipe_config->lane_count != 1)
> > return true;
> >
> > return false;
> > @@ -1234,7 +1235,7 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state)
> > {
> > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
> > + if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
>
> I'm probably missing something, but this change...
This should have been a separate change I suppose. What this is
currently asserting is DP-SST needs FEC to use DSC, but so does DP-MST
which this is totally forgetting to check. eDP is only case where we
can skip FEC.
>
>
> > return false;
> >
> > return intel_dsc_source_support(crtc_state) &&
> > @@ -1580,15 +1581,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > int pipe_bpp;
> > int ret;
> >
> > - pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > - intel_dp_supports_fec(intel_dp, pipe_config);
> > -
> > - if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > - return -EINVAL;
> > -
> > - if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > - return -EINVAL;
> > -
> > if (compute_pipe_bpp)
> > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
> > else
> > @@ -1615,6 +1607,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > pipe_config->port_clock = limits->max_rate;
> > pipe_config->lane_count = limits->max_lane_count;
> >
> > + pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > + intel_dp_supports_fec(intel_dp, pipe_config);
> > +
> > + if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > + return -EINVAL;
> > +
> > + if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > + return -EINVAL;
> > +
> > if (intel_dp_is_edp(intel_dp)) {
> > pipe_config->dsc.compressed_bpp =
> > min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
>
> ...and this code move are not explained in the commit message? How are
> they related?
This is moved becaue we need to compute lanel_count before we can
actually check it.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-09-13 14:41 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-02 14:38 [Intel-gfx] [PATCH 00/11] drm/i915: MST+DSC nukage and state stuff Ville Syrjala
2023-05-02 14:38 ` Ville Syrjala
2023-05-02 14:38 ` [Intel-gfx] [PATCH 01/11] drm/dp_mst: Fix fractional DSC bpp handling Ville Syrjala
2023-05-02 14:38 ` Ville Syrjala
2023-05-03 20:37 ` [Intel-gfx] " Lyude Paul
2023-05-03 20:37 ` Lyude Paul
2023-05-02 14:38 ` [Intel-gfx] [PATCH 02/11] drm/i915/mst: Remove broken MST DSC support Ville Syrjala
2023-05-02 14:38 ` Ville Syrjala
2023-05-02 14:38 ` Ville Syrjala
2023-05-03 7:17 ` [Intel-gfx] " Lisovskiy, Stanislav
2023-05-03 7:17 ` Lisovskiy, Stanislav
2023-05-03 7:17 ` Lisovskiy, Stanislav
2023-05-03 7:36 ` [Intel-gfx] " Lisovskiy, Stanislav
2023-05-03 7:36 ` Lisovskiy, Stanislav
2023-05-03 7:36 ` Lisovskiy, Stanislav
2023-05-03 11:07 ` [Intel-gfx] " Ville Syrjälä
2023-05-03 11:07 ` Ville Syrjälä
2023-05-03 11:07 ` Ville Syrjälä
2023-05-03 12:23 ` [Intel-gfx] " Lisovskiy, Stanislav
2023-05-03 12:23 ` Lisovskiy, Stanislav
2023-05-03 12:23 ` Lisovskiy, Stanislav
2023-06-15 22:11 ` [Intel-gfx] " Dave Airlie
2023-06-15 22:11 ` Dave Airlie
2023-06-15 22:11 ` Dave Airlie
2023-05-02 14:38 ` [Intel-gfx] [PATCH 03/11] drm/i915/mst: Read out FEC state Ville Syrjala
2023-05-02 14:38 ` Ville Syrjala
2023-05-25 7:56 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:38 ` [Intel-gfx] [PATCH 04/11] drm/i915: Fix FEC pipe A vs. DDI A mixup Ville Syrjala
2023-05-02 14:38 ` Ville Syrjala
2023-05-25 8:00 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [Intel-gfx] [PATCH 05/11] drm/i915: Check lane count when determining FEC support Ville Syrjala
2023-05-02 14:39 ` Ville Syrjala
2023-05-25 8:09 ` [Intel-gfx] " Luca Coelho
2023-09-13 14:41 ` Ville Syrjälä [this message]
2023-05-02 14:39 ` [Intel-gfx] [PATCH 06/11] drm/i915: Fix FEC state dump Ville Syrjala
2023-05-02 14:39 ` Ville Syrjala
2023-05-25 8:37 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [Intel-gfx] [PATCH 07/11] drm/i915: Split some long lines Ville Syrjala
2023-05-02 14:39 ` Ville Syrjala
2023-05-25 8:40 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [Intel-gfx] [PATCH 08/11] drm/i915: Introduce crtc_state->enhanced_framing Ville Syrjala
2023-05-02 14:39 ` Ville Syrjala
2023-05-03 11:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-05-03 11:36 ` Ville Syrjala
2023-05-25 9:51 ` [Intel-gfx] " Luca Coelho
2023-09-13 14:36 ` Ville Syrjälä
2023-05-02 14:39 ` [Intel-gfx] [PATCH 09/11] drm/i915: Stop spamming the logs with PLL state Ville Syrjala
2023-05-02 14:39 ` Ville Syrjala
2023-05-25 9:52 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [Intel-gfx] [PATCH 10/11] drm/i915: Drop some redundant eDP checks Ville Syrjala
2023-05-02 14:39 ` Ville Syrjala
2023-05-25 9:54 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [Intel-gfx] [PATCH 11/11] drm/i915: Reduce combo PHY log spam Ville Syrjala
2023-05-02 14:39 ` Ville Syrjala
2023-05-25 9:58 ` [Intel-gfx] " Luca Coelho
2023-05-02 15:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: MST+DSC nukage and state stuff Patchwork
2023-05-02 15:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-02 15:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-05-02 17:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: MST+DSC nukage and state stuff (rev2) Patchwork
2023-05-02 17:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-02 18:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-05-03 12:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: MST+DSC nukage and state stuff (rev3) Patchwork
2023-05-03 12:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-03 13:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-05-03 17:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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