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From: Oliver Upton To: Shameer Kolothum Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, zhukeqian1@huawei.com, jonathan.cameron@huawei.com, linuxarm@huawei.com Subject: Re: [RFC PATCH v2 3/8] KVM: arm64: Add some HW_DBM related pgtable interfaces Message-ID: References: <20230825093528.1637-1-shameerali.kolothum.thodi@huawei.com> <20230825093528.1637-4-shameerali.kolothum.thodi@huawei.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230825093528.1637-4-shameerali.kolothum.thodi@huawei.com> X-Migadu-Flow: FLOW_OUT Hi Shameer, On Fri, Aug 25, 2023 at 10:35:23AM +0100, Shameer Kolothum wrote: > From: Keqian Zhu > > This adds set_dbm, clear_dbm and sync_dirty interfaces in pgtable > layer. (1) set_dbm: Set DBM bit for last level PTE of a specified > range. TLBI is completed. (2) clear_dbm: Clear DBM bit for last > level PTE of a specified range. TLBI is not acted. (3) sync_dirty: > Scan last level PTE of a specific range. Log dirty if PTE is writeable. > > Besides, save the dirty state of PTE if it's invalided by map or > unmap. > > Signed-off-by: Keqian Zhu > Signed-off-by: Shameer Kolothum > --- > arch/arm64/include/asm/kvm_pgtable.h | 45 +++++++++++++ > arch/arm64/kernel/image-vars.h | 2 + > arch/arm64/kvm/hyp/pgtable.c | 98 ++++++++++++++++++++++++++++ > 3 files changed, 145 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > index 3f96bdd2086f..a12add002b89 100644 > --- a/arch/arm64/include/asm/kvm_pgtable.h > +++ b/arch/arm64/include/asm/kvm_pgtable.h > @@ -578,6 +578,51 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtable *pgt, u64 addr, u64 size, > */ > int kvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 addr, u64 size); > > +/** > + * kvm_pgtable_stage2_clear_dbm() - Clear DBM of guest stage-2 address range > + * without TLB invalidation (only last level). > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address from which to clear DBM, > + * @size: Size of the range. > + * > + * The offset of @addr within a page is ignored and @size is rounded-up to > + * the next page boundary. > + * > + * Note that it is the caller's responsibility to invalidate the TLB after > + * calling this function to ensure that the disabled HW dirty are visible > + * to the CPUs. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_clear_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size); > + > +/** > + * kvm_pgtable_stage2_set_dbm() - Set DBM of guest stage-2 address range to > + * enable HW dirty (only last level). > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address from which to set DBM. > + * @size: Size of the range. > + * > + * The offset of @addr within a page is ignored and @size is rounded-up to > + * the next page boundary. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_set_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size); > + > +/** > + * kvm_pgtable_stage2_sync_dirty() - Sync HW dirty state into memslot. > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address from which to sync. > + * @size: Size of the range. > + * > + * The offset of @addr within a page is ignored and @size is rounded-up to > + * the next page boundary. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_sync_dirty(struct kvm_pgtable *pgt, u64 addr, u64 size); > + > /** > * kvm_pgtable_stage2_wrprotect() - Write-protect guest stage-2 address range > * without TLB invalidation. > diff --git a/arch/arm64/kernel/image-vars.h b/arch/arm64/kernel/image-vars.h > index 35f3c7959513..2ca600e3d637 100644 > --- a/arch/arm64/kernel/image-vars.h > +++ b/arch/arm64/kernel/image-vars.h > @@ -68,6 +68,8 @@ KVM_NVHE_ALIAS(__hyp_stub_vectors); > KVM_NVHE_ALIAS(vgic_v2_cpuif_trap); > KVM_NVHE_ALIAS(vgic_v3_cpuif_trap); > > +KVM_NVHE_ALIAS(mark_page_dirty); > + This doesn't make any sense besides satisfying the linker. The hyp page table walkers will *never* need to mark a page as dirty. Consider adding a new function pointer to kvm_pgtable_mm_ops and only set it for the 'normal' stage-2 mm ops in mmu.c. > +static bool stage2_pte_writeable(kvm_pte_t pte) > +{ > + return pte & KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; > +} > + > +static void kvm_update_hw_dbm(const struct kvm_pgtable_visit_ctx *ctx, > + kvm_pte_t new) > +{ > + kvm_pte_t old_pte, pte = ctx->old; > + > + /* Only set DBM if page is writeable */ > + if ((new & KVM_PTE_LEAF_ATTR_HI_S2_DBM) && !stage2_pte_writeable(pte)) > + return; > + > + /* Clear DBM walk is not shared, update */ > + if (!kvm_pgtable_walk_shared(ctx)) { > + WRITE_ONCE(*ctx->ptep, new); > + return; > + } > + > + do { > + old_pte = pte; > + pte = new; > + > + if (old_pte == pte) > + break; > + > + pte = cmpxchg_relaxed(ctx->ptep, old_pte, pte); > + } while (pte != old_pte); > +} > + We don't need a separate walker for updating the DBM state in the page tables. Can't we treat it like any other permission bit and use something like kvm_pgtable_stage2_relax_perms()? Also, what is the purpose of retrying the update on a descriptor if the cmpxchg() fails? Everywhere else in the page table walker code we bail and retry execution since that is a clear indication of a race. In all likelihood the other vCPU thread was either trying to update DBM or service a permission fault. > static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > { > + if (kvm_pgtable_walk_hw_dbm(ctx)) { > + kvm_update_hw_dbm(ctx, new); > + return true; > + } > + Why are you trying to circumvent the primitive for setting stage-2 PTEs? > if (!kvm_pgtable_walk_shared(ctx)) { > WRITE_ONCE(*ctx->ptep, new); > return true; > @@ -952,6 +990,11 @@ static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx, > stage2_pte_executable(new)) > mm_ops->icache_inval_pou(kvm_pte_follow(new, mm_ops), granule); > > + /* Save the possible hardware dirty info */ > + if ((ctx->level == KVM_PGTABLE_MAX_LEVELS - 1) && > + stage2_pte_writeable(ctx->old)) > + mark_page_dirty(kvm_s2_mmu_to_kvm(pgt->mmu), ctx->addr >> PAGE_SHIFT); > + > stage2_make_pte(ctx, new); > > return 0; > @@ -1125,6 +1168,11 @@ static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx, > */ > stage2_unmap_put_pte(ctx, mmu, mm_ops); > > + /* Save the possible hardware dirty info */ > + if ((ctx->level == KVM_PGTABLE_MAX_LEVELS - 1) && > + stage2_pte_writeable(ctx->old)) > + mark_page_dirty(kvm_s2_mmu_to_kvm(mmu), ctx->addr >> PAGE_SHIFT); > + > if (need_flush && mm_ops->dcache_clean_inval_poc) > mm_ops->dcache_clean_inval_poc(kvm_pte_follow(ctx->old, mm_ops), > kvm_granule_size(ctx->level)); > @@ -1230,6 +1278,30 @@ static int stage2_update_leaf_attrs(struct kvm_pgtable *pgt, u64 addr, > return 0; > } > > +int kvm_pgtable_stage2_set_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size) > +{ > + int ret; > + u64 offset; > + > + ret = stage2_update_leaf_attrs(pgt, addr, size, KVM_PTE_LEAF_ATTR_HI_S2_DBM, 0, > + NULL, NULL, KVM_PGTABLE_WALK_HW_DBM | > + KVM_PGTABLE_WALK_SHARED); > + if (!ret) > + return ret; > + > + for (offset = 0; offset < size; offset += PAGE_SIZE) > + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa_nsh, pgt->mmu, addr + offset, 3); > + > + return 0; > +} > + > +int kvm_pgtable_stage2_clear_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size) > +{ > + return stage2_update_leaf_attrs(pgt, addr, size, > + 0, KVM_PTE_LEAF_ATTR_HI_S2_DBM, > + NULL, NULL, KVM_PGTABLE_WALK_HW_DBM); > +} > + > int kvm_pgtable_stage2_wrprotect(struct kvm_pgtable *pgt, u64 addr, u64 size) > { > return stage2_update_leaf_attrs(pgt, addr, size, 0, > @@ -1329,6 +1401,32 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, > return ret; > } > > +static int stage2_sync_dirty_walker(const struct kvm_pgtable_visit_ctx *ctx, > + enum kvm_pgtable_walk_flags visit) > +{ > + kvm_pte_t pte = READ_ONCE(*ctx->ptep); ctx->old is fetched in __kvm_pgtable_visit(), and the whole parallelization scheme for page table walkers depends on us being careful to read the PTE once per level. Do you need to reread it here? -- Thanks, Oliver From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61B3DCD37AD for ; Fri, 15 Sep 2023 22:23:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2RsKH4FFCiLyDU7mGLoJtH1JYLJL3xPl/iCV6hQybn8=; b=Jca5+VO5IvIueA YDp6LlfMtRFdTxFqBL5QQMIYz2X/Yz39Pm9rAIDP5STrAdxvKnMdG7zVr+InwvNOS9xGh6UZ42gaX iRq+8pN/1jKLdgG2pvaLqzHbnO2F0RMvNGP0iUqH4ZHYTrb319P2kmwxnaAfN7QL3fY+gPTE3lknG zt5SXSe7F0YutcWhDrZY9g3nak91aMzpdG0AJHt2saRmqR/bAgyd5lA9vp8nkTaxdhxXhi0OKBFoQ iu7lJW7ZH6rLgLaubizEmkYMveg+UVE4r20AurJgPHx6fUxqiuFvNzL5Lc10jU8JHc7HkKmw/AeyT 2jpG72lkG42usRym5NFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qhHDC-00BTyf-2o; Fri, 15 Sep 2023 22:22:54 +0000 Received: from out-216.mta0.migadu.com ([2001:41d0:1004:224b::d8]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qhHD9-00BTy4-2B for linux-arm-kernel@lists.infradead.org; Fri, 15 Sep 2023 22:22:54 +0000 Date: Fri, 15 Sep 2023 22:22:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1694816568; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=qzk1kWKQ5Jx8f4B0HOb4pSvibE/Fy1ssQI2BM7f0Yns=; b=ggGdDqrbvN9k7CtjcilAYWv5wrCp89MUGf1OzF2gAJbx3CswGYzxMPFAzN9/3b/XIorCmt iQ3uo4/LhlEAkzZsQjbMFpfPv6J+ppIZA2HYg03PbSwjI1aONLtMyUoxfssUbi1TySe444 9V6e//bPtYa+wMXakQW7uEEKCbC0+P8= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Shameer Kolothum Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, zhukeqian1@huawei.com, jonathan.cameron@huawei.com, linuxarm@huawei.com Subject: Re: [RFC PATCH v2 3/8] KVM: arm64: Add some HW_DBM related pgtable interfaces Message-ID: References: <20230825093528.1637-1-shameerali.kolothum.thodi@huawei.com> <20230825093528.1637-4-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230825093528.1637-4-shameerali.kolothum.thodi@huawei.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230915_152252_140434_9BFF3315 X-CRM114-Status: GOOD ( 33.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Shameer, On Fri, Aug 25, 2023 at 10:35:23AM +0100, Shameer Kolothum wrote: > From: Keqian Zhu > > This adds set_dbm, clear_dbm and sync_dirty interfaces in pgtable > layer. (1) set_dbm: Set DBM bit for last level PTE of a specified > range. TLBI is completed. (2) clear_dbm: Clear DBM bit for last > level PTE of a specified range. TLBI is not acted. (3) sync_dirty: > Scan last level PTE of a specific range. Log dirty if PTE is writeable. > > Besides, save the dirty state of PTE if it's invalided by map or > unmap. > > Signed-off-by: Keqian Zhu > Signed-off-by: Shameer Kolothum > --- > arch/arm64/include/asm/kvm_pgtable.h | 45 +++++++++++++ > arch/arm64/kernel/image-vars.h | 2 + > arch/arm64/kvm/hyp/pgtable.c | 98 ++++++++++++++++++++++++++++ > 3 files changed, 145 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > index 3f96bdd2086f..a12add002b89 100644 > --- a/arch/arm64/include/asm/kvm_pgtable.h > +++ b/arch/arm64/include/asm/kvm_pgtable.h > @@ -578,6 +578,51 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtable *pgt, u64 addr, u64 size, > */ > int kvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 addr, u64 size); > > +/** > + * kvm_pgtable_stage2_clear_dbm() - Clear DBM of guest stage-2 address range > + * without TLB invalidation (only last level). > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address from which to clear DBM, > + * @size: Size of the range. > + * > + * The offset of @addr within a page is ignored and @size is rounded-up to > + * the next page boundary. > + * > + * Note that it is the caller's responsibility to invalidate the TLB after > + * calling this function to ensure that the disabled HW dirty are visible > + * to the CPUs. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_clear_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size); > + > +/** > + * kvm_pgtable_stage2_set_dbm() - Set DBM of guest stage-2 address range to > + * enable HW dirty (only last level). > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address from which to set DBM. > + * @size: Size of the range. > + * > + * The offset of @addr within a page is ignored and @size is rounded-up to > + * the next page boundary. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_set_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size); > + > +/** > + * kvm_pgtable_stage2_sync_dirty() - Sync HW dirty state into memslot. > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address from which to sync. > + * @size: Size of the range. > + * > + * The offset of @addr within a page is ignored and @size is rounded-up to > + * the next page boundary. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_sync_dirty(struct kvm_pgtable *pgt, u64 addr, u64 size); > + > /** > * kvm_pgtable_stage2_wrprotect() - Write-protect guest stage-2 address range > * without TLB invalidation. > diff --git a/arch/arm64/kernel/image-vars.h b/arch/arm64/kernel/image-vars.h > index 35f3c7959513..2ca600e3d637 100644 > --- a/arch/arm64/kernel/image-vars.h > +++ b/arch/arm64/kernel/image-vars.h > @@ -68,6 +68,8 @@ KVM_NVHE_ALIAS(__hyp_stub_vectors); > KVM_NVHE_ALIAS(vgic_v2_cpuif_trap); > KVM_NVHE_ALIAS(vgic_v3_cpuif_trap); > > +KVM_NVHE_ALIAS(mark_page_dirty); > + This doesn't make any sense besides satisfying the linker. The hyp page table walkers will *never* need to mark a page as dirty. Consider adding a new function pointer to kvm_pgtable_mm_ops and only set it for the 'normal' stage-2 mm ops in mmu.c. > +static bool stage2_pte_writeable(kvm_pte_t pte) > +{ > + return pte & KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; > +} > + > +static void kvm_update_hw_dbm(const struct kvm_pgtable_visit_ctx *ctx, > + kvm_pte_t new) > +{ > + kvm_pte_t old_pte, pte = ctx->old; > + > + /* Only set DBM if page is writeable */ > + if ((new & KVM_PTE_LEAF_ATTR_HI_S2_DBM) && !stage2_pte_writeable(pte)) > + return; > + > + /* Clear DBM walk is not shared, update */ > + if (!kvm_pgtable_walk_shared(ctx)) { > + WRITE_ONCE(*ctx->ptep, new); > + return; > + } > + > + do { > + old_pte = pte; > + pte = new; > + > + if (old_pte == pte) > + break; > + > + pte = cmpxchg_relaxed(ctx->ptep, old_pte, pte); > + } while (pte != old_pte); > +} > + We don't need a separate walker for updating the DBM state in the page tables. Can't we treat it like any other permission bit and use something like kvm_pgtable_stage2_relax_perms()? Also, what is the purpose of retrying the update on a descriptor if the cmpxchg() fails? Everywhere else in the page table walker code we bail and retry execution since that is a clear indication of a race. In all likelihood the other vCPU thread was either trying to update DBM or service a permission fault. > static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > { > + if (kvm_pgtable_walk_hw_dbm(ctx)) { > + kvm_update_hw_dbm(ctx, new); > + return true; > + } > + Why are you trying to circumvent the primitive for setting stage-2 PTEs? > if (!kvm_pgtable_walk_shared(ctx)) { > WRITE_ONCE(*ctx->ptep, new); > return true; > @@ -952,6 +990,11 @@ static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx, > stage2_pte_executable(new)) > mm_ops->icache_inval_pou(kvm_pte_follow(new, mm_ops), granule); > > + /* Save the possible hardware dirty info */ > + if ((ctx->level == KVM_PGTABLE_MAX_LEVELS - 1) && > + stage2_pte_writeable(ctx->old)) > + mark_page_dirty(kvm_s2_mmu_to_kvm(pgt->mmu), ctx->addr >> PAGE_SHIFT); > + > stage2_make_pte(ctx, new); > > return 0; > @@ -1125,6 +1168,11 @@ static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx, > */ > stage2_unmap_put_pte(ctx, mmu, mm_ops); > > + /* Save the possible hardware dirty info */ > + if ((ctx->level == KVM_PGTABLE_MAX_LEVELS - 1) && > + stage2_pte_writeable(ctx->old)) > + mark_page_dirty(kvm_s2_mmu_to_kvm(mmu), ctx->addr >> PAGE_SHIFT); > + > if (need_flush && mm_ops->dcache_clean_inval_poc) > mm_ops->dcache_clean_inval_poc(kvm_pte_follow(ctx->old, mm_ops), > kvm_granule_size(ctx->level)); > @@ -1230,6 +1278,30 @@ static int stage2_update_leaf_attrs(struct kvm_pgtable *pgt, u64 addr, > return 0; > } > > +int kvm_pgtable_stage2_set_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size) > +{ > + int ret; > + u64 offset; > + > + ret = stage2_update_leaf_attrs(pgt, addr, size, KVM_PTE_LEAF_ATTR_HI_S2_DBM, 0, > + NULL, NULL, KVM_PGTABLE_WALK_HW_DBM | > + KVM_PGTABLE_WALK_SHARED); > + if (!ret) > + return ret; > + > + for (offset = 0; offset < size; offset += PAGE_SIZE) > + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa_nsh, pgt->mmu, addr + offset, 3); > + > + return 0; > +} > + > +int kvm_pgtable_stage2_clear_dbm(struct kvm_pgtable *pgt, u64 addr, u64 size) > +{ > + return stage2_update_leaf_attrs(pgt, addr, size, > + 0, KVM_PTE_LEAF_ATTR_HI_S2_DBM, > + NULL, NULL, KVM_PGTABLE_WALK_HW_DBM); > +} > + > int kvm_pgtable_stage2_wrprotect(struct kvm_pgtable *pgt, u64 addr, u64 size) > { > return stage2_update_leaf_attrs(pgt, addr, size, 0, > @@ -1329,6 +1401,32 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, > return ret; > } > > +static int stage2_sync_dirty_walker(const struct kvm_pgtable_visit_ctx *ctx, > + enum kvm_pgtable_walk_flags visit) > +{ > + kvm_pte_t pte = READ_ONCE(*ctx->ptep); ctx->old is fetched in __kvm_pgtable_visit(), and the whole parallelization scheme for page table walkers depends on us being careful to read the PTE once per level. Do you need to reread it here? -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel